Hi all,
the problems boiled down to two things:
- full MII and non-shared MII-management interface is not
currently supported for MCF5445x
- when a PHY returns id 0x0, matching for this ID results in
a lock-up in mcfmii.c
considering PHY ID 0x0 as broken anyways, I could get my board
to run w
On 26 Mar 2010 at 15:55, w.weg...@astro-kom.de wrote:
> phytype is matched against the last entry of phyinfo erroneously:
>
> phy_info_t phyinfo[] = {
> {0x0022561B, "AMD79C784VC"},/* AMD 79C784VC */
> [...]
> {0, 0}
> };
ouch, things are even worse... I did not quote enough of th
Hi,
On 26 Mar 2010 at 14:13, w.weg...@astro-kom.de wrote:
[...]
> When a command like dhcp times out and eth_init tries to switch to the other
> interface (FEC1) with eth_current->init(), U-Boot locks up. I still have to
> look
> further into this what exactly fails.
the lockup itself is caused
Hi all,
I still have problems with the ethernet on my custom MCF54452 board.
Here is my current configuration:
/* this is defined for M54455EVB in m68k/immap.h *sigh* */
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
#define CONFIG_NET_MULTI1
#define CONFIG_MII
2010 10:40 AM
To: John Schmoller; u-boot@lists.denx.de
Subject: Re: [U-Boot] several problems with ethernet on MCF5445x
Dear John,
On 23 Mar 2010 at 10:11, John Schmoller wrote:
> On Tue, 2010-03-23 at 15:50 +0100, w.weg...@astro-kom.de wrote:
> > I have a DP83848J PHY connected in MII m
Dear John,
On 23 Mar 2010 at 10:11, John Schmoller wrote:
> On Tue, 2010-03-23 at 15:50 +0100, w.weg...@astro-kom.de wrote:
> > I have a DP83848J PHY connected in MII mode to each of the FEC0
> > and FEC1 ports (seperate MDIO connection). Both PHYs are set to
> > address 0x0. *)
>
> Are you sure
On Tue, 2010-03-23 at 15:50 +0100, w.weg...@astro-kom.de wrote:
> Dear list,
>
> I am trying to get ethernet to work on my custom MCF54455 board
> and having some trouble.
>
> I have a DP83848J PHY connected in MII mode to each of the FEC0
> and FEC1 ports (seperate MDIO connection). Both PHYs ar
Dear list,
I am trying to get ethernet to work on my custom MCF54455 board
and having some trouble.
I have a DP83848J PHY connected in MII mode to each of the FEC0
and FEC1 ports (seperate MDIO connection). Both PHYs are set to
address 0x0. *)
In my config (basically copied from M54455EVB), I se
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