Wolfgang Denk schrieb:
> In message <[EMAIL PROTECTED]> you wrote:
>> You are right. 100 ms is too high, although it should be irrelevant for
>> a U-Boot command. Measurement showed, that some 100 microseconds would
>> be enough. Do you agree if I set the timeout value to 1 ms? Other proposals?
>
In message <[EMAIL PROTECTED]> you wrote:
>
> You are right. 100 ms is too high, although it should be irrelevant for
> a U-Boot command. Measurement showed, that some 100 microseconds would
> be enough. Do you agree if I set the timeout value to 1 ms? Other proposals?
Never say 100 ms is irrele
Jean-Christophe PLAGNIOL-VILLARD schrieb:
> On 16:50 Fri 04 Jul , Jens Gehrlein wrote:
>> On fast CPUs the time between two chip queries can become too short
>> to issue clear start and stop conditions. The bus seems to be blocked.
>> This cannot be compensated by just waiting for completed byt
On 16:50 Fri 04 Jul , Jens Gehrlein wrote:
> On fast CPUs the time between two chip queries can become too short
> to issue clear start and stop conditions. The bus seems to be blocked.
> This cannot be compensated by just waiting for completed byte transfer.
> The patch introduces polling of t
On fast CPUs the time between two chip queries can become too short
to issue clear start and stop conditions. The bus seems to be blocked.
This cannot be compensated by just waiting for completed byte transfer.
The patch introduces polling of the bus busy bit in the I2C
controller's status register
