On Wednesday 20 February 2008, Mike Nuss wrote:
On PPC440EPx without a bootstrap I2C EEPROM, the PLL can be reconfigured
after startup to change the speed of the clocks. This patch adds the
option CFG_PLL_RECONFIG. If this option is set to 667, the CPU
initialization code will reconfigure the
Mike,
On Wednesday 20 February 2008, Mike Nuss wrote:
don't you think this is a little bit to shortsighted?
There are many other parameters beyond the CPU clock that could be
modified in such a way. We have some code in the PMC440 board
code that sets up the PCI sync clock dynamically
On PPC440EPx without a bootstrap I2C EEPROM, the PLL can be reconfigured
after startup to change the speed of the clocks. This patch adds the
option CFG_PLL_RECONFIG. If this option is set to 667, the CPU
initialization code will reconfigure the PLL to run the system with a CPU
frequency of 667MHz
On PPC440EPx without a bootstrap I2C EEPROM, the PLL can be reconfigured after
startup in order to change the speed of the clocks. This patch adds the option
CONFIG_667MHZ. If set, it will set the clocks to run at full speed on a 667MHz
PPC440EPx without the need for an external EEPROM.
Matthias Fuchs wrote:
Hi Mike,
don't you think this is a little bit to shortsighted?
There are many other parameters beyond the CPU clock that could be
modified in such a way. We have some code in the PMC440 board
code that sets up the PCI sync clock dynamically dependant on
a GPIO
