Re: [USRP-users] No output from OOT RFNOC Module

2017-10-11 Thread Dario Pennisi via USRP-users
Hi, If your block is sending small amounts of bursty data the timeout being printed is irrelevant as it just indicates no data has been sent for a given time lapse not that no data has been received at all. Dario Pennisi On Wed, Oct 11, 2017 at 10:10 PM +0200, "John Medrano via

[USRP-users] Removing DC offset on USRP B200

2017-10-11 Thread Oliver Wayne via USRP-users
Hello, I've implemented a DDS signal on the USRP device. In radio_legacy.v, I input get_tx_I and get_tx_Q as my I and Q channels. always @(posedge radio_clk) begin tx[31:16] <= (run_tx) ? get_tx_I[31:16] : tx_idle[31:16]; // I channel tx[15:0] <= (run_tx) ? get_tx_Q[31:16] : tx_idle[15:0]; //

Re: [USRP-users] Frequency offset between two USRPs B210 synchronized with use of Octoclock-G

2017-10-11 Thread Piotr Krysik via USRP-users
Hi all, After discussion on IRC and few questions (by Brian Padalino and Marcus D. Leech), that made me not so sure about how I made the measurement, I found the reason for frequency offset. It wasn't fault of USRP B210 or broken cable providing 10MHz reference signal. The issue was a bit more

[USRP-users] RFNoC Block with 2 inputs and 1 output

2017-10-11 Thread Andrew Thommesen via USRP-users
Hi all, I am trying to create a custom RFNoC block with 2 inputs and 1 output. I have attached my block code as well as the XML files for the UHD and GNU radio integration. The block behaves as expected when I run the testbench. However, when synthesised and used within the GNU radio flowgraph

Re: [USRP-users] ADC Self-Test FAILED

2017-10-11 Thread Mark Koenig via USRP-users
Thank you for the follow up. Is this the only resolution? Thank you Mark From: Michael West Date: Tuesday, October 10, 2017 at 4:00 PM To: Mark Koenig Cc: "usrp-users@lists.ettus.com" Subject: Re:

Re: [USRP-users] Help to configure/install PCI-Express Connectivity Kit for X310

2017-10-11 Thread Neel Pandeya via USRP-users
Hello Daniele Disco: Unfortunately, at this time, the kernel driver for the PCIe Kit only supports up to kernel 4.2, and you are using kernel 4.10. Would you be able to downgrade you kernel, perhaps by using Ubuntu 14.04? We are working to add support for newer kernels to the PCIe driver, but I

[USRP-users] Help to configure/install PCI-Express Connectivity Kit for X310

2017-10-11 Thread Disco Daniele via USRP-users
Hi! With the X310 we have also taken the PCI-Express Connectivity Kit. Following the instruction reported here (http://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_hw) And going in the section : PCI Express (Desktop) that send to http://files.ettus.com/manual/page_ni_rio_kernel.html

[USRP-users] IQ samples being lost when using SOB/EOB

2017-10-11 Thread Felipe Augusto Pereira de Figueiredo via USRP-users
Dear All, I'm sending OFDM frames in a bursty manner, i.e., a have slots of 1 ms with 14 OFDM symbols. These 1 ms slots are transmitted from time to time and I'm using SOB and EOB to make it a busrty transmission. What I have noticed is that some samples at the beginning of the slot are being

Re: [USRP-users] RFNOC complex_multiplier not found

2017-10-11 Thread Nicolas Cuervo via USRP-users
Hello Kau-Uwe, You have to point your Makefile where the IP is located so that it can build it for simulation. You can base this on the Makefile for the FIR filter, for example [1], where the IP specific settings are introduced. In your specific use case, it should be something like:

Re: [USRP-users] additional Verilog file in OOT RFNoC block

2017-10-11 Thread Nicolas Cuervo via USRP-users
Hello Dixon, Daniel's suggestion works, but that would mean adding a hard-coded path into the fpga build system. It does the trick, but it is not recommended. The OOT module has its own Makefile.srcs that intends to contain all the HDL code that is required for the module. The procedure is the

[USRP-users] RFNOC complex_multiplier not found

2017-10-11 Thread Kai-Uwe Storek via USRP-users
Hey, if I use an instantiation of rfnoc-devel/usrp3/lib/rfnoc/cmul.v in my design, the compilation / elaboration process (make noc_block_myblock_tb) fails with: ERROR: [VRFC 10-2063] Module not found while processing module instance

Re: [USRP-users] RFNOC x300 Rx/Tx loopback

2017-10-11 Thread Daniel Rauschen via USRP-users
Update... I figured it out. The conversation "Re: [USRP-users] GRC + RFNoC + Radio Loopback" was kind of helpful. On 04.10.2017 11:29, Daniel Rauschen via USRP-users wrote: Hi, I am trying to do a Rx / Tx loopback test and I am stuck for days with it. For the sake of simplicity I

Re: [USRP-users] additional Verilog file in OOT RFNoC block

2017-10-11 Thread Daniel Rauschen via USRP-users
Hi Jim, try to add the file multTest.v (with the complete absolute path) in the Makefile.srcs located at .../uhd/fpga-src/usrp3/top/x300/. At least this worked for me. Best regards, Daniel On 11.10.2017 03:45, Dixon, James L via USRP-users wrote: Hi, I am trying to figure out how to add