[USRP-users] About the PCIe connection and drivers

2018-09-03 Thread Peng Wang via USRP-users
Hi all, I have couple of USRP X310 and also the PCIe connectivity kit. However, I found that the driver [1] says that it can only support up to kernel version 4.2.x. Since I am using ubuntu 18.04 with much newer kernel so I cannot install the driver. My questions would be: 1. What is the stat

[USRP-users] Feeding USRPN210 output stream to two hosts

2018-09-03 Thread Fabrizio Pollastri via USRP-users
Hi all, our configuration has one USRP N210 sending output to one host for signal processing. Since the host is able to process only 50% of wanted signal channels, one simple solution will be to add a second host and to send N210 data stream in parallel to both hosts. It is possible to do it

Re: [USRP-users] Feeding USRPN210 output stream to two hosts

2018-09-03 Thread Marcus D. Leech via USRP-users
On 09/03/2018 11:10 AM, Fabrizio Pollastri via USRP-users wrote: Hi all, our configuration has one USRP N210 sending output to one host for signal processing. Since the host is able to process only 50% of wanted signal channels, one simple solution will be to add a second host and to send N21

[USRP-users] Pulling in AXI_FFT into a OOT module and block

2018-09-03 Thread Rich Maes via USRP-users
Is there an example of modifying a out of tree (OOT) module and block to pull in a rfnoc library. Specifically I would like to pull in the AXI_FFT generated code and make my own custom FFT block. I can’t quite figure out how to modify the CMAKE files, (I assume that is the proper method) to re

Re: [USRP-users] sc12 on B2xx

2018-09-03 Thread Marcus D. Leech via USRP-users
On 09/03/2018 12:15 AM, Marcus D. Leech via USRP-users wrote: On 09/03/2018 12:11 AM, RizThon wrote: Thanks, I'll try to run it on some intel hardware ("Ettus Research recommends using the Intel Series 7, 8, and 9 USB controllers.") as well as on Linux. Concerning my question on SC12, namely

[USRP-users] Software changes for new FPGA registers B205

2018-09-03 Thread Chintan Patel via USRP-users
Hello, I have defined a new readback register in the FPGA in the b205_core file, adjacent to the lock state register. What is the least invasive function call/method in the UHD driver/software to be able to read this newly defined register? Thanks C ___

Re: [USRP-users] Pulling in AXI_FFT into a OOT module and block

2018-09-03 Thread Jon Pendlum via USRP-users
Hey Rich, Do you want to customize the FFT IP or use it as is? If you are using it as is, there is no need to do anything. All in-tree code and IP is automatically included as part of the FPGA build. If you want to customize it, I suggest copying the FFT IP into your OOT and using https://github.c

[USRP-users] Rx streaming to alternate destination

2018-09-03 Thread Horix On via USRP-users
I was following this thread below, and I wanted to see if anyone has been able to get X3x0, N310 streaming to a different IP/Port working? I am using RFNOC and have mostly followed this example: https://github.com/EttusResearch/uhd/blob/master/host/examples/rfnoc_rx_to_file.cpp But the rx_streame

Re: [USRP-users] Pulling in AXI_FFT into a OOT module and block

2018-09-03 Thread Rich Maes via USRP-users
I’d like to add a configurable decimator and some averaging logic to the output of the FFT. So I’ll be adding some new registers to the control bloc and verilog, but the overall core will still be very similar. I’ll take a look at the examples you reference below to see if that gets me going