On 30/05/2023 17:44, Brian Padalino wrote:
On Tue, May 30, 2023 at 5:32 PM Mena Ghebranious
wrote:
I apologize, I think I must be missing something. This is the
filter (Xilinx IP) I see implemented in the N320 master code:
On 30/05/2023 18:17, Ashton Palacios wrote:
My research group recently got an Ettus X410. We are wanting to
connect to it through two MT27800 NICs on our server. We are able to
set up the IP addresses on the server and running uhd_find_devices
shows the USRP having the correct IP address that
My research group recently got an Ettus X410. We are wanting to connect to
it through two MT27800 NICs on our server. We are able to set up the IP
addresses on the server and running uhd_find_devices shows the USRP having
the correct IP address that we are expecting. When we go to run the
On Tue, May 30, 2023 at 5:32 PM Mena Ghebranious wrote:
> I apologize, I think I must be missing something. This is the filter
> (Xilinx IP) I see implemented in the N320 master code:
>
>
> https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/top/n3xx/dboards/rh/n3xx.v#L3431
>
This HBF
I apologize, I think I must be missing something. This is the filter
(Xilinx IP) I see implemented in the N320 master code:
https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/top/n3xx/dboards/rh/n3xx.v#L3431
We are planning on running various sample rates running from 1 to possibly
On Tue, May 30, 2023 at 4:42 PM Mena Ghebranious wrote:
> I don't see any bypass logic in the FPGA code, but in any case, the N320
> only supports three master clock rates, none of which is our desired
> sampling rate:
>
>
I don't see any bypass logic in the FPGA code, but in any case, the N320
only supports three master clock rates, none of which is our desired
sampling rate:
https://kb.ettus.com/USRP_N300/N310/N320/N321_Getting_Started_Guide#Supported_Sample_Rates
On Tue, May 30, 2023 at 11:44 AM Brian Padalino
On Tue, May 30, 2023 at 2:27 PM Mena Ghebranious wrote:
> Yes, bypassing the DUC was discussed among our team, but as far as I can
> tell, there is no way to configure the bypass via the UHD/USRP API - it
> would require an FPGA mod.
>
If you set the input rate to the radio to be the master
Yes, bypassing the DUC was discussed among our team, but as far as I can
tell, there is no way to configure the bypass via the UHD/USRP API - it
would require an FPGA mod.
On Tue, May 30, 2023 at 10:38 AM Brian Padalino wrote:
> On Tue, May 30, 2023 at 11:15 AM Mena Ghebranious
> wrote:
>
>>
On Tue, May 30, 2023 at 11:15 AM Mena Ghebranious wrote:
> If possible, I'd like to hear what the R team thinks - I have worked
> with designs in the past where the TX timing lines up and there are no
> samples cut off.
>
> On Tue, May 30, 2023 at 8:08 AM Marcus D. Leech
> wrote:
>
>> On
On 30/05/2023 12:03, Piotr Krysik wrote:
Hello
I've got a similar issue: completely new USRP X410 that doesn't react
to power button.
More specifically, there is a little sign of life - it constantly
prints something like this on UART that I suppose is a port of STM32
microcontroller:
---
Hello
I've got a similar issue: completely new USRP X410 that doesn't react to
power button.
More specifically, there is a little sign of life - it constantly prints
something like this on UART that I suppose is a port of STM32
microcontroller:
--- UART initialized after reboot ---
[Reset
On 30/05/2023 11:13, Mena Ghebranious wrote:
If possible, I'd like to hear what the R team thinks - I have worked
with designs in the past where the TX timing lines up and there are no
samples cut off.
I already have a feeler into R on this. But historically it has
"always been done this
If possible, I'd like to hear what the R team thinks - I have worked with
designs in the past where the TX timing lines up and there are no samples
cut off.
On Tue, May 30, 2023 at 8:08 AM Marcus D. Leech
wrote:
> On 30/05/2023 11:02, Mena Ghebranious wrote:
> > Hi Marcus,
> >
> > I took a
On 30/05/2023 11:02, Mena Ghebranious wrote:
Hi Marcus,
I took a closer look at the end of my transmission; what originally
appeared to be a lack of symmetry between the start and end delays is
actually a cutoff of 31 samples at the end of the transmission - in
other words, I'm missing the
Hi Marcus,
I took a closer look at the end of my transmission; what originally
appeared to be a lack of symmetry between the start and end delays is
actually a cutoff of 31 samples at the end of the transmission - in other
words, I'm missing the 31 samples at the end of the TX that I put into the
16 matches
Mail list logo
