Re: [USRP-users] Filter Error

What is the "fa" frequency you're trying to configure? Given you're using 1 MHz of sampling frequency, fa cannot be greater than 500 kHz. On Wed, Jun 5, 2019 at 11:24 AM Sneha vasan via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi everyone, > > Can anybody guide me on this???.. I am using

Re: [USRP-users] PPS to custom RFNoC block

Hey Cherif, I have no experience with this whatsoever, but taking the X310 code as an example, I see that PPS is an input signal to x300_core.v, where the RFNoC blocks are instantiated. I'd assume you could route this directly to your custom block. Regards, Leo. On Tue, Apr 9, 2019 at 6:32 AM C

Re: [USRP-users] Two RFNOC tx blocks timing and Bus

Hi Xingjian, If I understood your problem correctly, you are expecting two equal streams to arrive at the same time on the output, but you have an AXI Crossbar in the middle. This is a packet-based router, so it is hard to predict its behavior timing-wise, and I don't think this would be the right

[USRP-users] Vivado license for 10 GbE

Hey everyone, Upon building my own custom RFNoC images for an X310 using Vivado GUI, I'm getting a critical warning stating the following: "Evaluation License Warning: This design contains one or more evaluation cores that will cease to function after a certain period of time. This design should N

Re: [USRP-users] Control several USRPs via switch

Hey Maria, If I'm not wrong, USRPs have default static IP addresses, which are specific to the FPGA image you've loaded onto them. Perhaps if you're using more than one in the same network domain there's being a collision and you need to change one of the board's IP default IP addresses first? Jus

Re: [USRP-users] Maximum bandwidth of the X-series

Sorry for the typo, I meant to write 6.4 Gbps. Regards, Leo On Wed, Jan 30, 2019, 13:24 Leandro Echevarría wrote: > Hello María, > > The A/D converters on these daughterboards are complex samplers, which > means you get the full 200 MHz of bandwidth and no aliasing will occur. > > As for the

Re: [USRP-users] Maximum bandwidth of the X-series

Hello María, The A/D converters on these daughterboards are complex samplers, which means you get the full 200 MHz of bandwidth and no aliasing will occur. As for the computer requirements, one 32-bits-wide 200 MSps stream equals 6.4 GBps (800 MBps), so you'll need a PCIe or NVMe SSD drive at lea

Re: [USRP-users] Utilisation of core RFNoC Image

Hey Andrew, Have you confirmed the available resources are not enough for your purpose? If so, I'd suggest you run the build command with the GUI option on, implement the design using the Vivado interface, and run a post-implementation utilization report to see which blocks are consuming the most.

Re: [USRP-users] SBX-120 daughterboard calibration on X310

Made it work. I was not specifying the subdev corectly, and using the argument --subdev "B:0" did the job. Maybe it can be of help to someone. Thanks anyway! Leo On Thu, Jan 17, 2019 at 11:40 AM Leandro Echevarría wrote: > Hey everybody, > > I've got two SBX-120 daughterboards on an USRP X310

[USRP-users] SBX-120 daughterboard calibration on X310

Hey everybody, I've got two SBX-120 daughterboards on an USRP X310. When running uhd_cal_tx_dc_offset, it automatically calibrates the first of the two listed, and I cannot get it to do it also for the second one. How should I go about this? I couldn't find a way to select channel/DB in uhd_cal_tx

Re: [USRP-users] RFNoC FPGA clear_tx_seqnum behavior

Hey Jason, I haven't followed your thread thoroughly, but I thought I'd comment something that could be of help, even though the code you included is apparently from July: I wouldn't use a standard synchronizer for a one-clock pulse signal such as clear_tx_seqnum. Instead, I'd recommend using Ettu

[USRP-users] SBX-120 transmit power

Hey folks, The Knowledge Base webpage for the SBXs daughterboards [1] mentions that their maximum output power is 100 mW (20 dBm), and that the transmit gains range goes from 0 to 31.5 dB. Does this mean 20 dBm is the power output when the gain is set to 31.5 dB? Also, the X300 Starting Guide [2

[USRP-users] Ready to custom block de-asserted and questions about RX streaming

Hey folks, I designed a custom block that writes and reads data to the external DDR3 RAM. I'm using NoC Shell + 64-bit-wide CHDR framers and deframers, all of them within the bus_clk (there clock domain crossing to the 300 MHz DDR clock happens closer to the AXI DMA block). The writing portion see

Re: [USRP-users] RFNoC TX Examples

Hey Ryan, Thanks a lot! I actually ended up doing pretty much the exact same things you described, and came up with a piece of code very similar to yours. Yours is neater though, so I will keep it ;-). Regards, Leo On Wed, Sep 19, 2018 at 7:52 PM Ryan Marlow wrote: > Hey Leo, > I haven't seen

[USRP-users] RFNoC TX Examples

Hey everybody, Is there anywhere I could find C++ examples of a TX stream using RFNoC blocks? The latest rnoc-devel commit only has two RX examples, and I cannot seem to replicate the behavior from that. Thanks, Leo ___ USRP-users mailing list USRP-use

Re: [USRP-users] Issues with modified x310 FPGA image

I solved the issue, so I'm gonna say really quickly what went wrong: I was defining a greater number of Computation Engines than the number of blocks I was actually instantiating, so the Crossbar was expecting two more blocks to be connected (and hence the timeouts, I guess from trying to ping the

[USRP-users] Issues with modified x310 FPGA image

Hey folks, I'm working on a modified rfnoc-devel FPGA image for the x310, which involves doing custom RFNoC blocks and modifying some of the existing too. In the last test I made, I synthesized instantiating two of my custom blocks (one of them twice), plus some other modification to the AXI DMA

Re: [USRP-users] Use same RFNoC block twice

Great Brian, thanks a lot for your help! On Fri, Aug 31, 2018 at 4:19 PM Brian Padalino wrote: > On Fri, Aug 31, 2018 at 2:54 PM Leandro Echevarría via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Hey everybody, >> >> I've got a question. I have

[USRP-users] Use same RFNoC block twice

Hey everybody, I've got a question. I have a RFNoC block that has a unique NoC ID as a parameter, but is instantiated twice in my design (same situation as the Radio Cores or DDC/DUC blocks, that share the same NoC ID but are connected to different Crossbar ports when included more than once in th

Re: [USRP-users] About CHDR packet size

bly/disassembly would have occurred at the periphery of the FPGA > and all logic would then be required to support 2^16 packet sizes had the > implementation fully addressed the max possible architectural CHDR packet > size. > > -Ian > > > On Aug 1, 2018, at 3:38 PM, Leandr

Re: [USRP-users] About CHDR packet size

Hello Nick, That's the spirit of my question: why couldn't you break up a CHDR packet over multiple Ethernet frames? I understand it is common for Ethernet to break up an IP packet (which would also have a 16-bits field for packet size in its header) into fragments, but limiting the size of the CH

[USRP-users] About CHDR packet size

Hey everybody, I'll somehow repeat a question I asked here a couple of months ago, to see again if I can get some guiding. Hope you understand: The CHDR packet length field in the CHDR header is 16 bits (i.e. 65536 bytes theoretical max length), but by doing Wireshark captures and playing with th

Re: [USRP-users] distinguishing FPGA images

Rob, Addressing your first question, I would modify (or add) one setting_reg in your modified NoC Block, and instantiate the parameter "at_reset" (which is usually not included in the instantiation) with a known value (such as a localparam defined previously in the file or in an include file). Ch

Re: [USRP-users] Computer for X310

ate were high enough, >> you have enough memory, and you use SSD disks. >> >> Did you end up buying the system? If so, how has it performed? >> >> --​Neel Pandeya >> >> >> >> On 6 September 2017 at 06:33, Leandro Echevarría via USRP-users < >&

Re: [USRP-users] BRAM usage of the X300/X310 design

Hey Nives, If it's of any help: on an X310, my utilization report for a design including a DMA_FIFO, both radio cores, two DDCs and two DUCs uses around 42% of the FPGA's Block RAM resources, and if I take out the DDCs and DUCs, the usage drops to around 34%. Regards, Lei On Mon, May 21, 2018 a

Re: [USRP-users] CHDR and UDP packets

As a follow up to this: I've just done a wireshark capture of a stream, using the benchmark rate @ 200 MSps and the CHDR dissector included in the repositories, and I see every data CHDR packet has a size of 1F40 (8000 bytes): is this to avoid Ethernet fragmentation from the get-go? Should I do th

[USRP-users] CHDR and UDP packets

Hey everybody, I'm planning on building the CHDR packets myself for some blocks of my own (or at least proviing my own header when using the AXI Wrapper), and I've got two simple questions about this: 1. If I specify a CHDR length of , is there a determined timeframe within which I HAVE to co

[USRP-users] RFNoC support for maint branch

Hey everybody, I was able to make an example block by installing uhd+gr-ettus with PyBombs rfnoc-devel recipes, then using rfnocmodtool, generating .xml and .v files, and then "compiling and installing" the block from the previously generated makefiles. I also included the block in the FPGA code,

[USRP-users] About RFNoC development

Hey everybody, I've begun working on an X310 board, and I need to make modifications to the Verilog code to include my own code. My strength is on HDL design, but I lack experience on the software part. I've got some questions (in order from most urgent to more annecdotical) I'd very much apprecia

Re: [USRP-users] USRP-users help needed

Dear Joe, All the FPGA Verilog code is available in the Github Repo: https://github.com/EttusResearch/fpga I believe the B200mini falls within the USRP3 category. And about the decimation itself, after a quick search through the repo folders I found a DSP block that seems to indicate decimation i

Re: [USRP-users] Computer for X310

el Pandeya > > > > On 6 September 2017 at 06:33, Leandro Echevarría via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Hey everybody, >> >> We're about to buy a new computer to work with an USRP X310, using dual >> 10 Gbps SFP+ Etherne

Re: [USRP-users] cannot ping

Hello Seah, That's certainly not a trivial task. If you want the devices to behave as two addressable network interfaces with a link between them, I believe you'd have to modify a whole lot of things (the UHD driver -or directly bypass it-, the way TCP/IP/Ethernet framing is done inside the FPGA,

Re: [USRP-users] cannot ping

Seah, are you saying that you're trying to get a wireless link working between both USRP devices? If that is the case, and you are not implementing a full protocol and handshaking between them in the RF domain, they will not behave as intended (i.e., as a pair of wireless CPEs, such as Ubiquiti Nan

Re: [USRP-users] cannot ping

Hello ChongSeah, Can you explain a little more about what your network configuration looks like? Maybe a drawing of all the network interfaces with their respective IPs and subnet masks may help us understand the problem better. How are the computers connected? And how are the N210s connected to

[USRP-users] Computer for X310

Hey everybody, We're about to buy a new computer to work with an USRP X310, using dual 10 Gbps SFP+ Ethernet connections through a PCIe card (we need to reach full 200 MSps). I've seen at Ettus you "use a desktop computer with a quadcore i7, 8+ GB of DDR3". We are planning on buying an AMD platfo

Re: [USRP-users] Very Close - Trying to Connect B210 Using VMware

Hi Matheou, When using Virtualbox and a X310 connected through USB, every time the Ettus rebooted after an image updating I had to go the Virtualbox menu and select the device again from the list of connected USB devices to make the virtual machine recognize it. Perhaps you're skipping this step?