Dear all,
I combined noc_block_siggen and noc_block_fir_filter to transmit pulses with
its samples can be updated using a E312. I borrowed some code from the
axi_fir_filter.v for sample update. The updated samples are stored in block
memory. The transmitter works well for both channels. However
Hi,
Is there a way to use timed command for E312 rfnoc siggen module for setup gain?
I am trying something like below. Is this the right way? Thank you.
uhd::time_spec_t cmd_time = time_ref +
uhd::time_spec_t(i*256/28e6*10*2000*10);
ctrl_siggen_ch0->set_command_time(cmd_ti
UHD_INSTALL(TARGETS ${example_name} RUNTIME DESTINATION
${PKG_LIB_DIR}/examples COMPONENT examples)
ENDFOREACH(example_source)
From: USRP-users on behalf of Xingjian
Chen via USRP-users
Sent: Monday, September 16, 2019 8:36:45 PM
To: USRP-users
Hi there,
Good evening. I have a special need to embed python code in CPP for my E312
because I want to do some data processing and generate a waveform. In order to
do so, must be included as header, however it requires changing the
gcc compiler argument. Could someone point me in which file I
but I don't see where you
assign it.
On Wed, Apr 24, 2019 at 7:15 AM Xingjian Chen via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
Hi Guys,
Good morning. I am wondering how to insert an EOB in Verilog code to the radio.
What I have tried is cvita_hdr_modify as below. I th
Hi Guys,
Good morning. I am wondering how to insert an EOB in Verilog code to the radio.
What I have tried is cvita_hdr_modify as below. I think just change EOB bit
should put the tx radio into the idle state. However, when the EOB changed, my
E312 returned an error as below. There is a regist
Dear All,
For E312 RFNOC, I have a question about updating time for both tx and rx chain.
I would like to send and receive pulses at a certain time simultaneously(As
long as they happen at the same time, it is fine).
I have already set this up by playing with vita time in FPGA and time_spec in
Dear all,
What is the difference for vita_time between the vita_time in noc_shell and
axi_wrapper in a RFNOC module?
I noticed that there is vita_time input for noc_shell, but also a vita_time can
be included in the axi_wrapper input s_axis_data_tuser. I guess that for
noc_shell, the vita_time
Hi Leo,
I get your idea. Thank you.
references:
http://ettus.80997.x6.nabble.com/USRP-users-vita-time-td9675.html
https://conferences.sigcomm.org/sigcomm/2013/papers/srif/p45.pdf
https://corvid.io/2017/04/22/stupid-rfnoc-tricks-loopback/
https://files.ettus.com/manual/page_rtp.html
https://s
Dear All,
I am doing FPGA debugging with an E312. I have two exactly same signal
generation RFNOC modules run simultaneously. The waveform is triggered by a
reference clock generated in Verilog at the same time. What I found is that
when the waveform went from RFNOC module to noc_block_radio_cor
Dear all,
I have some questions about how to trigger RFNOC receiver. I have a module
detecting the rising edge of a fixed clock. I used that clock to trigger Tx and
Rx modules. Now the transmit RFNOC module is working properly but the receive
module gives me non-deterministic m_axis_data_tvalid
ers on behalf of Xingjian
Chen via USRP-users
Sent: Tuesday, March 26, 2019 11:25:05 AM
To: USRP-users@lists.ettus.com
Cc: usrp-users-boun...@lists.ettus.com
Subject: [USRP-users] Two receive channels simultaneously for E312
Dear all,
Good morning. What is the right way to use two receive chann
Dear all,
Good morning. What is the right way to use two receive channels simultaneously
for E312 with RFNOC radio and UHD cpp control? Thank you in advance.
There is only a receiver radio block and I have set up the rx streamer:
rx_radio_ctrl->set_rx_streamer(true, rx_chan);
rx_radio_ct
Hi,
Is there any method can control the timing for the RFNOC Replay Block in X310?
I tried adding time spec but the transmitter failed to start. In fact, as long
as I set "stream_cmd.stream_now = false;" then, the transmitter will not turn
on unless set it back to true and power restart the X310
From: USRP-users on behalf of Xingjian
Chen via USRP-users
Sent: Wednesday, January 9, 2019 10:37:20 PM
To: USRP-users@lists.ettus.com
Subject: [USRP-users] Fw: E312 rfnoc_radio_loopback.cpp FPGA image
Dear all,
I am working on the rfnoc_radio_loopback.cpp example in the
Dear all,
I am working on the rfnoc_radio_loopback.cpp example in the latest UHD
repository on my E312. This loopback example seems requires two radio blocks.
May I know how to build the FPGA image to have two radios blocks on the device
such as Radio_0 and Radio_1? Currently, I can build an im
Hi there,
I find the "file_source" block in RFNoC for X310. Is there any example or
tutorial how to use it by either UHD C++ or GNURadio? I am new to RFNoC and
trying to get started with transmitting a waveform from a source file in a host
computer. Thank you!
__
n order to have "bash" as default.
As an additional example, when I run "echo $0" in my shell it returns "zsh",
because that is the shell that I'm am running in my terminal, and the
testbenches run just fine, because my default shell is bash (as seen with ls -l
Hi,
When I follow the instruction from "Getting Started with RFNoC Development" web
and youtube video "RFNoC Getting Started Video Tutorial", everything was smooth
until making the gain block testbench. Here is the error I got after the step
"make noc_block_gain_tb":
"/bin/sh: 1: source: not
Hi,
I am interested in controlling LO frequency using E312 in such a way that timed
command must be used. However, as far as I know, E312 doesn't support timed
command for RF front end. So I am thinking if I could write some simple modules
in Verilog HDL setting up LO frequency. I am wondering
Hi,
Is there any way for E312 to self-calibrate? I found there is IQ imbalance in
amplitude and dc offset showing in the recorded signal's real and imaginary
part. But it seems that its daughter board is not supported for
self-calibration. Any idea to solve this? Thank you very much.
__
Hi,
I am trying to utilize the digital loopback to check transmitted signal before
DAC in my E312. May I know what is the C++ command to enable the digital
loopback? How to set the SR_LOOPBACK register? In the radio.v, it says,
// Set this register to loop TX data directly to RX data.
s
Hi,
I added some IP cores in E312 FPGA codes and have to delete one radio channel
for saving some resources such as block RAMs. I notice that the UHD cpp files
always checking both radio channels. What is the proper way to stop it if only
one channel is used? I was trying to modify e300_impl.cp
Hi,
How consistent is B200mini can be in terms of signal amplitude if I restart the
board? I am sending and getting chirp pulses at the same time by a B200mini. I
found that if I restart the board every time before the loopback measurement,
and comparing pulses between measurements, the amplit
Hi,
I am trying to set up a user register for a B200mini. There are several posts
related to this. Such as
1.
http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2017-April/024739.html
2.
http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2017-April/024739.html
Are there any cle
25 matches
Mail list logo
