g
when I pasted it here.
----- Original Message - Subject: Re: [USRP-users] rfnoc build
works for E310, doesn't meet timing with X310
From: "EJ Kreinar"
Date: 11/8/18 9:09 am
To: "Jason Matusiak"
Cc: "USRP-users@lists.ettus.com"
ad of
>> being elegant, I went with easy to code up.
>>
>>
>>
>> The block's title is a little misleading, it basically keeps M vectors
>> out of N vectors. So if the vector size is 512, and M==2 and N==10. I
>> will pass through 1024 samples, and th
and instead of
> being elegant, I went with easy to code up.
>
>
>
> The block's title is a little misleading, it basically keeps M vectors out
> of N vectors. So if the vector size is 512, and M==2 and N==10. I will
> pass through 1024 samples, and then dump the next
ples. Then wash, rinse,
repeat. The verilog is attached since I was having trouble keeping formatting
when I pasted it here.
- Original Message ----- Subject: Re: [USRP-users] rfnoc build
works for E310, doesn't meet timing with X310
From: "EJ Kreinar"
Dat
Hi Jason,
That actually makes sense to me... Bus clk on the e310 is usually 50 MHz if
I remember correctly (and if it didn't change), and the max radio_clk is
something like 64ish MHz.
Max clock rates on the x310 are, I believe, more like 200-215 MHz. So logic
in the x310 nominally needs to settl
Hi Jason,
The longer run times might be explained by the tool struggling to meet
timing. I can't say off the top of my head what's wrong without looking at
the timing report. Do you have an updated post_route_timing_summary.rpt
file yet? Buried in there it should say exactly what's not meeting tim
OK, this has befuddled me for 3 days and I can't seem to get past it. I have a
prefix that seems to work fine.
Here are my working steps for building a bitfile on an E310:
cd /opt/gnuradio/e300/src/uhd/fpga-src/usrp3/tools/scripts
source ../../top/e300/setupenv.sh
./uhd_image_builder.py kee
