Just to clarify the issue, ce was correct for other targets, it just
doesn't work on E-series, which is an oversight in the getting started
guide. Changing it to rfnoc_chdr is a good solution for E310.
Thanks,
Wade
On Thu, Feb 18, 2021 at 7:54 AM Aaron Rossetto via USRP-users <
usrp-users@lists.
On Thu, Feb 18, 2021 at 7:28 AM Mike via USRP-users <
usrp-users@lists.ettus.com> wrote:
That is a typo in AN-400 that should probably be fixed.
>
Indeed it is! Good catch, and my apologies for the inconvenience. Glad you
found the resolution.
I've filed an issue on GitHub to update the applicat
Aaron,
Yes, that is the solution. I saw that when looking at another YAML file
in the source folders. That is a typo in AN-400 that should probably be
fixed. In the section describing adding a FFT block to the receive chain:
clk_domains:
...
# As before, we still connect our F
On Tue, Feb 16, 2021 at 10:15 AM Mike via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Any ideas?
Try changing the clock domain connection to your FFT block to this:
- { srcblk: _device_, srcport: rfnoc_chdr,dstblk: fft0, dstport:ce
}
Does that allow rfnoc_image_builder to complet
Hi,
I'm building a new FPGA image for E310 based on the yaml file
"e310_rfnoc_image_core.yml". I'm adding a FFT block per the
instructions in "Getting_Started_with_RFNoC_in_UHD_4.0".
However, when I run:
rfnoc_image_builder -y ./e310_with_fft.yml -t E310
I get the error:
[ERR] 1 unresolve
