In old X-Gene Storm firmware and DT, secure mode addresses have been
mentioned in GICv2 node. In this case maintenance interrupt is used
instead of EOI HW method.
This patch checks the GIC Distributor Base Address to enable EOI quirk
for old firmware.
Ref:
http://lists.xen.org/archives/html/xen-d
Hi Ian,
Subject: s/HSR/HCR/
On 31/03/2015 12:07, Ian Campbell wrote:
This traps variety of implementation defined registers, so add a note
to the default case of the respective handler.
Signed-off-by: Ian Campbell
Other than the typo in the subject:
Reviewed-by: Julien Grall
Regards,
-
Hi Ian,
On 31/03/2015 12:07, Ian Campbell wrote:
While annotating ACTLR I noticed that we don't appear to handle the
64-bit version of this trap. Do so and annotate everything.
While Linux doesn't use ACTLR_EL1 on aarch64, another OS may use it.
I'm not sure if we should consider it as a poss
On Friday 27 March 2015 11:30 PM, Jaggi, Manish wrote:
From: Julien Grall
Sent: Friday, March 27, 2015 7:05 PM
To: Jaggi, Manish; Xen Devel; Stefano Stabellini; Ian Campbell;
prasun.kap...@cavium.com; Kumar, Vijaya
Subject: Re: [PATCH v1 1/3] xen/arm: smmu: Ren
flight 50329 linux-linus real [real]
http://logs.test-lab.xenproject.org/osstest/logs/50329/
Failures :-/ but no regressions.
Regressions which are regarded as allowable (not blocking):
test-amd64-i386-freebsd10-i386 7 freebsd-install fail like 50276
test-amd64-i386-freebsd10-amd6
Hi Ian,
On 31/03/2015 12:07, Ian Campbell wrote:
Add explicit handler for 64-bit CP14 accesses, with more relevant
debug message (as per other handlers) and to provide a place for the
comment.
It's a bit strange to name the patch "Annotate..." while the main change
is 64-bit CP14 accesses.
On 02/04/2015 18:19, Ian Campbell wrote:
On Thu, 2015-04-02 at 17:01 +0100, Ian Campbell wrote:
On Thu, 2015-04-02 at 16:50 +0100, Ian Campbell wrote:
Writing to the bottom half (e.g. w0) of a register implicitly clears the
top half, IIRC, so I think a kernel is unlikely to want to do this,
Hi Ian,
On 31/03/2015 12:07, Ian Campbell wrote:
Signed-off-by: Ian Campbell
---
xen/arch/arm/traps.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index ba120e5..21bef01 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/trap
Hi Ian,
Subject: s/PCTR/CPTR/
On 31/03/2015 12:07, Ian Campbell wrote:
Signed-off-by: Ian Campbell
---
xen/arch/arm/traps.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 9cdbda8..ba120e5 100644
--- a/xen/arch/arm/trap
Hi Ian,
On 31/03/2015 12:07, Ian Campbell wrote:
Signed-off-by: Ian Campbell
---
xen/arch/arm/traps.c | 32
xen/include/asm-arm/cpregs.h |4
xen/include/asm-arm/sysregs.h |1 +
3 files changed, 37 insertions(+)
diff --git a/xen/arc
On Fri, Apr 03, 2015 at 11:12:15PM +0100, Ian Murray wrote:
> On 03/04/15 21:02, Konrad Rzeszutek Wilk wrote:
> > If we cannot find the domain - log an error (and still
> > continue returning an error).
> Forgive me if I am misunderstanding the effect of this patch (I tried to
> find the original r
On Sat, Apr 04, 2015 at 04:14:24AM +0200, Dario Faggioli wrote:
> From: Chao Peng
>
> Switching RMID from previous vcpu to next vcpu only needs to write
> MSR_IA32_PSR_ASSOC once. Write it with the value of next vcpu is enough,
> no need to write '0' first. Idle domain has RMID set to 0 and becau
On Sat, Apr 04, 2015 at 04:14:33AM +0200, Dario Faggioli wrote:
> Just print it.
>
> Signed-off-by: Dario Faggioli
> ---
> xen/arch/x86/psr.c |3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
> index c902625..0f2a6ce 100644
> -
Hi Ian,
On 31/03/2015 12:07, Ian Campbell wrote:
We set CNTHCTL_EL2.EL1PCTEN and therefore according to ARMv8 (DDI
0487A.d) D1-1510 Table D1-60 we are not trapping this.
Signed-off-by: Ian Campbell
Reviewed-by: Julien Grall
Regards,
--
Julien Grall
Hi Ian,
On 31/03/2015 12:07, Ian Campbell wrote:
Signed-off-by: Ian Campbell
---
xen/arch/arm/traps.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 1c9cf21..cc5b8dd 100644
--- a/xen/arch/arm/traps
On Sat, Apr 04, 2015 at 04:14:41AM +0200, Dario Faggioli wrote:
> This allows for a new item to be passed as part of the psr=
> boot option: "percpu_cmt". If that is specified, Xen tries,
> at boot time, to associate an RMID to each core.
>
> XXX This all looks rather straightforward, if it weren'
Hi Ian,
On 31/03/2015 12:07, Ian Campbell wrote:
I was unable to find an ARMv8 ARM reference to this, so refer to the
GIC Architecture Specification instead.
ARMv8 ARM does cover other ways of trapping these accesses via
ICH_HCR_EL2 but we don't use those and they trap additional registers
as w
On Fri, Apr 03, 2015 at 03:52:30PM -0700, Andy Lutomirski wrote:
> [cc: Boris and Konrad. Whoops]
>
> On Fri, Apr 3, 2015 at 3:51 PM, Andy Lutomirski wrote:
> > We don't use irq_enable_sysexit on 64-bit kernels any more. Remove
Is there an commit (or name of patch) that explains why
32-bit-us
Hi Ian,
On 01/04/2015 10:30, Ian Campbell wrote:
On Tue, 2015-03-31 at 17:48 +0100, Stefano Stabellini wrote:
If it helps we could add a couple of comments on top of the structs in
smmu.c to explain the meaning of the fields, like:
/* iommu_domain, not to be confused with a Xen domain */
I
Hi Ian,
On 31/03/2015 12:07, Ian Campbell wrote:
Gather the affected handlers in a single place per trap type.
Signed-off-by: Ian Campbell
---
xen/arch/arm/traps.c | 71 ++
1 file changed, 60 insertions(+), 11 deletions(-)
diff --git a/xen/
On Mon, Apr 6, 2015 at 7:10 AM, Konrad Rzeszutek Wilk
wrote:
> On Fri, Apr 03, 2015 at 03:52:30PM -0700, Andy Lutomirski wrote:
>> [cc: Boris and Konrad. Whoops]
>>
>> On Fri, Apr 3, 2015 at 3:51 PM, Andy Lutomirski wrote:
>> > We don't use irq_enable_sysexit on 64-bit kernels any more. Remove
flight 50330 qemu-upstream-4.5-testing real [real]
http://logs.test-lab.xenproject.org/osstest/logs/50330/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-i386-pair 17 guest-migrate/src_host/dst_host fail REGR. vs. 36517
Tests w
On 04/05/2015 07:09 AM, Emil Condrea wrote:
Enables deep quote execution for vtpmmgr which can not be started
using locality 2. The VTPM_ORD_GET_QUOTE command is backwards
compatible. When receives flags=0 from vTPM it extends additional
information into the PCRs as it did before.
Even without
Hi
I want to remove entry of a given page in the shadow page table so that
when the next time the guest access to the page there is page fault.
Here is what I try to do:
1. I have a timer which wake up every 30 seconds and remove entry in
the shadow by calling
sh_remove_all_mappings(d->vcpu[0
On 06/04/2015 16:29, Andy Lutomirski wrote:
> On Mon, Apr 6, 2015 at 7:10 AM, Konrad Rzeszutek Wilk
> wrote:
>> On Fri, Apr 03, 2015 at 03:52:30PM -0700, Andy Lutomirski wrote:
>>> [cc: Boris and Konrad. Whoops]
>>>
>>> On Fri, Apr 3, 2015 at 3:51 PM, Andy Lutomirski wrote:
We don't use irq
On 04/06/2015 01:44 PM, Andrew Cooper wrote:
On 06/04/2015 16:29, Andy Lutomirski wrote:
On Mon, Apr 6, 2015 at 7:10 AM, Konrad Rzeszutek Wilk
wrote:
On Fri, Apr 03, 2015 at 03:52:30PM -0700, Andy Lutomirski wrote:
[cc: Boris and Konrad. Whoops]
On Fri, Apr 3, 2015 at 3:51 PM, Andy Lutomir
Hi Pranav,
Thank you for the patch.
On 06/04/2015 10:54, Pranavkumar Sawargaonkar wrote:
In old X-Gene Storm firmware and DT, secure mode addresses have been
mentioned in GICv2 node. In this case maintenance interrupt is used
instead of EOI HW method.
This patch checks the GIC Distributor Base
On Mon, Apr 6, 2015 at 11:30 AM, Boris Ostrovsky
wrote:
>
> On 04/06/2015 01:44 PM, Andrew Cooper wrote:
>>
>> On 06/04/2015 16:29, Andy Lutomirski wrote:
>>>
>>> On Mon, Apr 6, 2015 at 7:10 AM, Konrad Rzeszutek Wilk
>>> wrote:
On Fri, Apr 03, 2015 at 03:52:30PM -0700, Andy Lutomirski w
On 04/06/2015 04:03 PM, Andy Lutomirski wrote:
On Mon, Apr 6, 2015 at 11:30 AM, Boris Ostrovsky
wrote:
On 04/06/2015 01:44 PM, Andrew Cooper wrote:
On 06/04/2015 16:29, Andy Lutomirski wrote:
On Mon, Apr 6, 2015 at 7:10 AM, Konrad Rzeszutek Wilk
wrote:
On Fri, Apr 03, 2015 at 03:52:30PM -0
xc_numainfo() is not expected to be used on a hot path and therefore
hypercall buffer management can be pushed into libxc. This will simplify
life for callers.
Also update error logging macros.
Signed-off-by: Boris Ostrovsky
---
Changes in v6:
* Dropped separate NULL buffer tests in xc_numainfo
Changes in v6:
* PCI topology interface changes: no continuations, userspace will be dealing
with "unfinished" sysctl (patches 2 and 5)
* Unknown device will cause ENODEV in sysctl
* No NULL tests in libxc
* Loop control initialization fix (similar to commit 26da081ac91a)
* Other minor changes (s
.. and use this new interface to display it along with CPU topology
and NUMA information when 'xl info -n' command is issued
The output will look like
...
cpu_topology :
cpu:coresocket node
0: 000
...
device topology:
device node
Signed-off-by: Boris Ostrovsky
---
Changes in v6:
* Dropped continuations, the sysctl now returns after 64 iteration if necessary
* -ENODEV returned if device is not found
* sysctl's first_dev is now expected to be used by userspace to continue the
query
* Added XSM hooks
docs/misc/xsm-flask.t
A number of changes to XEN_SYSCTL_numainfo interface:
* Make sysctl NUMA topology query use fewer copies by combining some
fields into a single structure and copying distances for each node
in a single copy.
* NULL meminfo and distance handles are a request for maximum number
of nodes (num_n
xc_cputopoinfo() is not expected to be used on a hot path and therefore
hypercall buffer management can be pushed into libxc. This will simplify
life for callers.
Also update error reporting macros.
Signed-off-by: Boris Ostrovsky
---
Changes in v6:
* Dropped NULL buffer test in xc_cputopoinfo()
flight 50332 xen-4.3-testing real [real]
http://logs.test-lab.xenproject.org/osstest/logs/50332/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-i386-freebsd10-i386 8 guest-start fail REGR. vs. 36755
Regressions which
> -Original Message-
> From: Konrad Rzeszutek Wilk [mailto:konrad.w...@oracle.com]
> Sent: Friday, April 03, 2015 9:37 PM
> To: Wu, Feng
> Cc: Tian, Kevin; Zhang, Yang Z; xen-devel@lists.xen.org; k...@xen.org;
> jbeul...@suse.com
> Subject: Re: [Xen-devel] [RFC v1 12/15] vmx: Properly han
Hi --
I've been trying to get nested virtualization working with Xen so that I
could boot Windows and use Hyper-V related features, however I have not had
much success. Using Windows 8.1 or Windows 2012r2, I'm able to install
Windows, select and install Hyper-V features, and start rebooting.
Howe
This patch is based on the code sent out by Peter Zijstra as part
of his queue spinlock patch to provide a hashing function with open
addressing. The lfsr() function can be used to return a sequence of
numbers that cycle through all the bit patterns (2^n -1) of a given
bit width n except the value
This patch adds the necessary Xen specific code to allow Xen to
support the CPU halting and kicking operations needed by the queue
spinlock PV code.
Signed-off-by: Waiman Long
---
arch/x86/xen/spinlock.c | 63 ---
kernel/Kconfig.locks|2 +-
2
Provide a separate (second) version of the spin_lock_slowpath for
paravirt along with a special unlock path.
The second slowpath is generated by adding a few pv hooks to the
normal slowpath, but where those will compile away for the native
case, they expand into special wait/wake code for the pv v
The current code for PV lock hash table processing will panic the
system if pv_hash_find() can't find the desired hash bucket. However,
there is no check to see if there is more than one entry for a given
lock which should never happen.
This patch adds a pv_hash_check_duplicate() function to do th
In the pv_scan_next() function, the slow cmpxchg atomic operation is
performed even if the other CPU is not even close to being halted. This
extra cmpxchg can harm slowpath performance.
This patch introduces the new mayhalt flag to indicate if the other
spinning CPU is close to being halted or not
v14->v15:
- Incorporate PeterZ's v15 qspinlock patch and improve upon the PV
qspinlock code by dynamically allocating the hash table as well
as some other performance optimization.
- Simplified the Xen PV qspinlock code as suggested by David Vrabel
.
- Add benchmarking data for 3.19 ker
From: Peter Zijlstra (Intel)
We use the regular paravirt call patching to switch between:
native_queue_spin_lock_slowpath() __pv_queue_spin_lock_slowpath()
native_queue_spin_unlock()__pv_queue_spin_unlock()
We use a callee saved call for the unlock function which reduces the
Before this patch, a CPU may have been kicked twice before getting
the lock - one before it becomes queue head and once before it gets
the lock. All these CPU kicking and halting (VMEXIT) can be expensive
and slow down system performance, especially in an overcommitted guest.
This patch add a new
This patch makes the necessary changes at the x86 architecture
specific layer to enable the use of queue spinlock for x86-64. As
x86-32 machines are typically not multi-socket. The benefit of queue
spinlock may not be apparent. So queue spinlock is not enabled.
Currently, there is some incompatibi
Currently, atomic_cmpxchg() is used to get the lock. However, this
is not really necessary if there is more than one task in the queue
and the queue head don't need to reset the tail code. For that case,
a simple write to set the lock bit is enough as the queue head will
be the only one eligible to
This patch introduces a new generic queue spinlock implementation that
can serve as an alternative to the default ticket spinlock. Compared
with the ticket spinlock, this queue spinlock should be almost as fair
as the ticket spinlock. It has about the same speed in single-thread
and it can be much
This patch adds the necessary KVM specific code to allow KVM to
support the CPU halting and kicking operations needed by the queue
spinlock PV code.
Signed-off-by: Waiman Long
---
arch/x86/kernel/kvm.c | 43 +++
kernel/Kconfig.locks |2 +-
2 files c
This is a preparatory patch that extracts out the following 2 code
snippets to prepare for the next performance optimization patch.
1) the logic for the exchange of new and previous tail code words
into a new xchg_tail() function.
2) the logic for clearing the pending bit and setting the loc
From: Peter Zijlstra (Intel)
When we detect a hypervisor (!paravirt, see qspinlock paravirt support
patches), revert to a simple test-and-set lock to avoid the horrors
of queue preemption.
Signed-off-by: Peter Zijlstra (Intel)
Signed-off-by: Waiman Long
---
arch/x86/include/asm/qspinlock.h |
From: Peter Zijlstra (Intel)
Because the qspinlock needs to touch a second cacheline (the per-cpu
mcs_nodes[]); add a pending bit and allow a single in-word spinner
before we punt to the second cacheline.
It is possible so observe the pending bit without the locked bit when
the last owner has ju
From: Peter Zijlstra (Intel)
When we allow for a max NR_CPUS < 2^14 we can optimize the pending
wait-acquire and the xchg_tail() operations.
By growing the pending bit to a byte, we reduce the tail to 16bit.
This means we can use xchg16 for the tail part and do away with all
the repeated compxch
flight 50333 xen-4.4-testing real [real]
http://logs.test-lab.xenproject.org/osstest/logs/50333/
Failures and problems with tests :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
build-armhf 3 host-install(3) broken REGR. vs. 502
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