Thank you
I understand your answer
Thanks !!
-Original Message-
From: "Stefano Stabellini"
To: "신정섭";
Cc: ; "Stefano
Stabellini"; "Ian
Campbell";
Sent: 2015-04-22 (수) 23:41:53
Subject: Re: virq injection probelem in Xen ARM 4.5
On Wed, 22 A
HI
I might find the VIRQ injection in Xen ARM 4.5 and fix with simple way.
Check please.
Problem
- In Xen ARM 4.5, SPI's pending_irq structure could be accessed simultaneously
from each pCPU.
Reason
- When inject SPI VIRQ to domain0, Xen ARM 4.5 set bit HW(31bit) bit in list
register. so do
efano Stabellini"<stefano.stabell...@eu.citrix.com>
To: "신정섭"<supsup5...@naver.com>;
Cc: "Stefano Stabellini"<stefano.stabell...@eu.citrix.com>; "Ian
Campbell"<ian.campb...@citrix.com>; <xen-devel@lists.xen.org>;
Sent: 2015-04-21 (화)
;s vcpu0
and Xen ARM 4.5 cannot inject spi to domain0's vcpu1.
Right?
And is this reason ARM 4.5 don't use maintanance interrupt?
Thanks
-Original Message-
From: "Stefano Stabellini"<stefano.stabell...@eu.citrix.com>
To: "신정섭"<supsu
;s vcpu on any
pcpu.
But int Xen4.5 vgic_vcpu_inject_irq() can inject SPI on only pcpu that receive
SPI from GICD.
Right?
-Original Message-
From: "Stefano Stabellini"<stefano.stabell...@eu.citrix.com>
To: "신정섭"<supsup5...@naver.com>;
Cc: "Ian Camp
pbell"<ian.campb...@citrix.com>
To: "신정섭"<supsup5...@naver.com>;
Cc: <xen-devel@lists.xen.org>; "Stefano
Stabellini"<stefano.stabell...@eu.citrix.com>;
Sent: 2015-04-17 (금) 18:49:39
Subject: Re: [Xen-devel] Is it ok to routing periperal irq to
I'm studying periperal irq routing to Domain0's vCPU
I'm testing on Arndale Broad and Domain 0 has 2 vCPU.
So Xen can select vcpu0 or vcpu1 to inject periperal irq.
I tested periperal routing on Xen 4.4.1 and it works well.
But I tested periperal routing on Xen 4.5.0 but irq dosen't works wel
t;<ian.campb...@citrix.com>;
Cc: "신정섭"<supsup5...@naver.com>; <xen-devel@lists.xen.org>;
"Stefano Stabellini"<stefano.stabell...@eu.citrix.com>;
Sent: 2015-04-15 (수) 20:59:53
Subject: Re: [Xen-devel] Question. Inject virq to Domain on Xen ARM.
On Wed, 15
HI
I have a question about Inject virq to Domain on Xen ARM.
Function 'vgic_vcpu_inject_irq' is inject virq to target vcpu.
At the end of vgic_vcpu_inject_irq, like below
--
running = v->is_running;
vcpu_unblock(v);
if ( running && v !=
Very simple reason...
I see.
Thanks.
-Original Message-
From: "Stefano Stabellini"<stefano.stabell...@eu.citrix.com>
To: "신정섭"<supsup5...@naver.com>;
Cc: <xen-devel@lists.xen.org>; <t...@xen.org>;
Sent: 2015-03-09 (월) 20:07:5
HI.
I'm now modifying GIC in Xen 4.5.0.
I have some question about lock of pending_irq struct in Xen ARM.
pending_irq of SGI and PPI is stored in 'vcpu struct'. (IRQ num 0 ~ 31)
pending_irq of SPI is stored in 'domain struct'. (IRQ num 32 ~ )
For accessing pending_irq struct, Xen use 'irq_to_
HI.
I'm now modifying GIC in Xen 4.5.0.
I have some question about lock of pending_irq struct in Xen ARM.
pending_irq of SGI and PPI is stored in 'vcpu struct'. (IRQ num 0 ~ 31)
pending_irq of SPI is stored in 'domain struct'. (IRQ num 32 ~ )
For accessing pending_irq struct, Xen use 'irq_to_
Hi
I'm studying about Xen 4.4.0 and Xen 4.5.0 on ARM
I have some questions about Interrupt and event channel on ARM.
1.In Xen 4.4.X and Xen 4.5.0 (GIC v2), all pirq(physical irq) are go to pcpu0
(physical cpu). After pirq, Xen run in pcpu0 only inject virq(virtual irq) to
vcpu0 of Dom0.I th
Hi
I'm studying about Xen 4.4.0 and Xen 4.5.0 on ARM
I have some questions about Interrupt and event channel on ARM.
1.In Xen 4.4.X and Xen 4.5.0 (GIC v2), all pirq(physical irq) are go to pcpu0
(physical cpu). After pirq, Xen run in pcpu0 only inject virq(virtual irq) to
vcpu0 of Dom0.I th
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