On physical machine EPC is exposed in ACPI table via "INT0E0C". Although EPC
can be discovered by CPUID but Windows driver requires EPC to be exposed in
ACPI table as well. This patch exposes EPC in ACPI table.
Signed-off-by: Kai Huang
---
tools/firmware/hvmloader/ut
assed to xc_cpuid_apply_policy.
xc_cpuid_apply_policy is extended to support SGX CPUID. If hypervisor doesn't
report SGX feature in host type cpufeatureset, then using 'epc' parameter
results in domain creation failure as SGX cannot be supported.
Signed-off-by: Kai Huang
---
tools/libxc/inc
fo. EPC base and size are also added to
'xc_dom_image' in order to add EPC to e820 table. EPC base is calculated
internally.
Signed-off-by: Kai Huang
---
tools/libxc/include/xc_dom.h | 4
tools/libxl/libxl_create.c | 9 +
tools/libxl/libxl_dom.c | 30
A new 'p2m_epc' type is added for EPC mapping type. Two wrapper functions
set_epc_p2m_entry and clear_epc_p2m_entry are also added for further use.
Signed-off-by: Kai Huang
---
xen/arch/x86/mm/p2m-ept.c | 3 +++
xen/arch/x86/mm/p2m.c | 41
Currently Xen only has non-cacheable version of ioremap. Although EPC is
reported as reserved memory in e820 but it can be mapped as cacheable. This
patch adds ioremap_cache (cacheable version of ioremap).
Signed-off-by: Kai Huang
---
xen/arch/x86/mm.c | 15 +--
xen/include/xen
e from toolstack via XEN_DOMCTL_set_cpuid,
so domain's EPC pages are also populated in XEN_DOMCTL_set_cpuid, after
receiving valid EPC base and size. Failure to populate EPC (such as there's
no enough free EPC pages) results in domain creation failure by making
XEN_DOMCTL_set_cpuid return er
lid. Used when domain
goes to S3-S5, or being destroyed.
- hvm_destroy_epc # destroy and free domain's EPC.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/sgx.c | 315 +
xen/arch/x86/hvm/vmx/vmx.c | 3 +
xen/
om L2 guest,
we simply inject it to L1, otherwise the ENCLS VMEXIT is unexpected in L0
and we simply crash the domain.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmx.c | 10 ++
xen/arch/x86/hvm/vmx/vvmx.c| 11 +++
xen/include/asm-x86/hvm/vmx/vmcs.h | 1 +
xen/in
VMX adds new bit to both exit_reason and GUEST_INTERRUPT_STATE to indicate
whether VMEXIT happens in Enclave. Several instructions are also invalid or
behave differently in enclave according to SDM. This patch handles those
cases.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmx.c
If ENCLS VMEXIT is not present then we cannot support SGX virtualization.
This patch detects presence of ENCLS VMEXIT. A Xen boot boolean parameter
'sgx' is also added to manually enable/disable SGX.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmcs.c| 17
EPC is destroyed when power state goes to S3-S5. Emulate this behavior.
A new function s3_suspend is added to hvm_function_table for this purpose.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/hvm.c| 3 +++
xen/arch/x86/hvm/vmx/vmx.c| 7 +++
xen/include/asm-x86/hvm/hvm.h | 3
scheduling, etc, as well), so currently only
one EPC is supported.
Dedicated files sgx.c and sgx.h are added (under vmx directory as SGX is Intel
specific) for bulk of above SGX detection code detection code, and for further
SGX code as well.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vm
ll 'struct epc_page' will
be in an array which is allocated during SGX initialization. Entire EPC is also
mapped to Xen's virtual address so that each EPC page's virtual address can be
calculated by base virtual address + offset.
Signed-off-by: Kai Huang
in guest, vcpu's virtual IA32_SGXLEPUBKEYHASHn
will be update to physical MSRs when vcpu is scheduled in.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/sgx.c | 194 +
xen/arch/x86/hvm/vmx/vmx.c | 24 +
xen/include/asm-x86/cpuf
, or
by PV ENCLS but it is really not necessary at this stage. And currently SGX
is only exposed to HAP HVM domain (we can add for shadow in the future).
SGX Launch Control is also exposed in CPU featureset for HVM domain. SGX
Launch Control depends on SGX.
Signed-off-by: Kai Huang
---
xen/include
napshot SGX guest by either:
- Suspend guest before snapshot (s3-s5). This works for all guests but
requires user to manually susppend guest.
- Issue an hypercall to destroy guest's EPC in save_vm. This only works for
Linux and Windows but doesn't require user interve
Since PML series were merged (but disabled by default) we have conducted lots of
PML tests (live migration, GUI display) and PML has been working fine, therefore
turn it on by default.
Document of PML command line is adjusted accordingly as well.
Signed-off-by: Kai Huang
Tested-by: Robert Hu
On 11/27/2015 04:35 PM, Jan Beulich wrote:
On 27.11.15 at 08:57, wrote:
Since PML series were merged (but disabled by default) we have conducted lots of
PML tests (live migration, GUI display) and PML has been working fine, therefore
turn it on by default.
Well, I'm not really opposed, but i
Since PML series were merged (but disabled by default) we have conducted lots of
PML tests (live migration, GUI display) and PML has been working fine, therefore
turn it on by default.
Signed-off-by: Kai Huang
Tested-by: Robert Hu
Tested-by: Xudong Hao
---
In case you might want some specific
Hi Kevin,
Would you comment on the two patches?
Thanks,
-Kai
On 10/20/2015 10:34 AM, Kai Huang wrote:
Patch 1 is the v2 of defering enabling of EPT A/D bit until PML get enabled,
with comments from Jan in v1 addressed. Patch 2 is coding style fix of
for_each_vcpu to existing PML functions
According to Jan's comments, also fix the coding style of for_each_vcpu in
existing PML functions.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmcs.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
ded ASSERT of domain having been paused to ept_flush_pml_buffers to make
it consistent with ept_enable{disable}_pml.
Sanity live migration and GUI display were tested on Broadwell Machine.
Signed-off-by: Kai Huang
Suggested-by: Jan Beulich
---
xen/arch/x86/hvm/vmx/vmcs.c
Patch 1 is the v2 of defering enabling of EPT A/D bit until PML get enabled,
with comments from Jan in v1 addressed. Patch 2 is coding style fix of
for_each_vcpu to existing PML functions according to Jan.
Kai Huang (2):
x86/ept: defer enabling of EPT A/D bit until PML get enabled.
x86/vmx
extra feature for
every
domain when we're not meaning to use it (yet).
Sanity live migration and GUI display were tested on Broadwell Machine.
Signed-off-by: Kai Huang
Signed-off-by: Jan Beulich
There's so little in this patch that came from me that I don't think this is
warranted; but
anity live migration and GUI display were tested on Broadwell Machine.
Signed-off-by: Kai Huang
Signed-off-by: Jan Beulich
---
xen/arch/x86/hvm/vmx/vmcs.c| 24
xen/arch/x86/mm/p2m-ept.c | 24
xen/include/asm-x86/hvm/vmx/vmcs.h | 2 +
On 10/15/2015 03:35 PM, Kai Huang wrote:
On 10/15/2015 03:11 PM, Jan Beulich wrote:
On 15.10.15 at 08:42, wrote:
Thanks for your comments Jan. Actually I am not happy with combining
with EPT A/D bit update with PML enabling to single function. After
thinking again, how about adding a
On 10/15/2015 03:11 PM, Jan Beulich wrote:
On 15.10.15 at 08:42, wrote:
Thanks for your comments Jan. Actually I am not happy with combining
with EPT A/D bit update with PML enabling to single function. After
thinking again, how about adding a separate vmx function (ex,
vmx_domain_update_eptp
On 10/14/2015 05:26 PM, Jan Beulich wrote:
On 14.10.15 at 11:08, wrote:
After some thinking, just set/clear p2m->ept.ept_ad is not enough -- we
also need to __vmwrite it to VMCS's EPTP, and then call ept_sync_domain.
Ah, yes, this makes sense of course.
I have verified attached patch can w
efer the latter, please provide comments.
Thanks,
-Kai
On 10/14/2015 09:19 AM, Kai Huang wrote:
Hi Jan,
Our QA tested this patch but this patch broke PML. Neither GUI display
(video ram tracking also uses PML) nor live migration works. I'll
investigate what's wrong and get back to y
Hi Jan,
Our QA tested this patch but this patch broke PML. Neither GUI display
(video ram tracking also uses PML) nor live migration works. I'll
investigate what's wrong and get back to you.
Thanks,
-Kai
On 09/30/2015 08:45 PM, Kai Huang wrote:
On Wed, Sep 30, 2015 at 5:54 PM, J
On 10/02/2015 05:36 PM, Wei Liu wrote:
On Wed, Sep 30, 2015 at 01:25:49PM +0100, Wei Liu wrote:
On Wed, Sep 30, 2015 at 05:36:22AM -0600, Jan Beulich wrote:
Since commit 191b3f3344ee ("p2m/ept: enable PML in p2m-ept for
log-dirty"), the A and D bits of EPT paging entries are set
unconditional
gt; anyway, i.e. hardware will pick up the new setting the next time
>>> each vCPU of the guest gets scheduled.
>>>
>>> Signed-off-by: Jan Beulich
>>> Cc: Kai Huang
>>> ---
>>> VT-x maintainers, Kai: Me lacking the hardware to test this, may
On Mon, Sep 28, 2015 at 10:09 PM, Jan Beulich wrote:
On 28.09.15 at 14:39, wrote:
>> --- a/xen/arch/x86/mm/p2m-ept.c
>> +++ b/xen/arch/x86/mm/p2m-ept.c
>> @@ -34,6 +34,8 @@
>>
>> #include "mm-locks.h"
>>
>> +static bool_t __read_mostly cpu_has_ept_ad;
>
> This should be
> #define cpu_has_ep
setting the flag should be
> sufficient - the domain is required to be paused for PML enabling
> anyway, i.e. hardware will pick up the new setting the next time
> each vCPU of the guest gets scheduled.
>
> Signed-off-by: Jan Beulich
> Cc: Kai Huang
> ---
> VT-x maintainers, K
On 09/24/2015 05:10 PM, Tim Deegan wrote:
At 01:02 -0600 on 24 Sep (1443056566), Jan Beulich wrote:
On 23.09.15 at 17:46, wrote:
At 16:18 +0100 on 23 Sep (1443025126), Wei Liu wrote:
With the discussion still not finalised I'm a bit worried that this
issue will block the release.
I think w
On 05/04/2015 03:52 PM, Jan Beulich wrote:
On 04.05.15 at 09:46, wrote:
On 04/27/2015 02:56 PM, Jan Beulich wrote:
Kai Huang 04/25/15 5:00 PM >>>
On Fri, Apr 24, 2015 at 10:33 PM, Jan Beulich wrote:
On 24.04.15 at 10:19, wrote:
+}
+
+custom_param("ept", parse
On 05/04/2015 03:40 PM, Tian, Kevin wrote:
From: Tim Deegan [mailto:t...@xen.org]
Sent: Thursday, April 30, 2015 7:04 PM
At 16:19 +0800 on 24 Apr (1429892368), Kai Huang wrote:
v2->v3:
- Merged v2 patch 02 (document change) to patch 01 as a single patch, and
changed new parame
On 04/27/2015 02:56 PM, Jan Beulich wrote:
Kai Huang 04/25/15 5:00 PM >>>
On Fri, Apr 24, 2015 at 10:33 PM, Jan Beulich wrote:
On 24.04.15 at 10:19, wrote:
+}
+
+custom_param("ept", parse_ept_param);
And a superfluous blank line would want to be dropped here.
Sure. W
Thanks Tim!
On Thu, Apr 30, 2015 at 7:04 PM, Tim Deegan wrote:
> At 16:19 +0800 on 24 Apr (1429892368), Kai Huang wrote:
>> v2->v3:
>>
>> - Merged v2 patch 02 (document change) to patch 01 as a single patch, and
>> changed new parameter description as sug
On Fri, Apr 24, 2015 at 10:33 PM, Jan Beulich wrote:
On 24.04.15 at 10:19, wrote:
>> --- a/xen/arch/x86/hvm/vmx/vmcs.c
>> +++ b/xen/arch/x86/hvm/vmx/vmcs.c
>> @@ -64,6 +64,36 @@ integer_param("ple_gap", ple_gap);
>> static unsigned int __read_mostly ple_window = 4096;
>> integer_param("ple
This patch adds help functions to enable/disable PML, and flush PML buffer for
single vcpu and particular domain for further use.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmcs.c| 179 +
xen/include/asm-x86/hvm/vmx/vmcs.h | 9 ++
2 files
nctions to enable/disable PML and flush PML
buffers. The new functions are named to be generic to cover potential futher
PML-like features for other platforms.
Signed-off-by: Kai Huang
---
xen/arch/x86/mm/hap/hap.c | 29 +
xen/arch/x86/mm/p2m.
A top level EPT parameter "ept=" and a sub boolean "opt_pml_enabled"
are added to control PML. Other booleans can be further added for any other EPT
related features.
The document description for the new parameter is also added.
Signed-off-by: Kai Huang
---
docs/misc/xen-c
It's possible domain still remains in log-dirty mode when it is about to be
destroyed, in which case we should manually disable PML for it.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmx.c | 8
1 file changed, 8 insertions(+)
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen
for vcpu (being current, or being non-running and unrunnable) to
vmx_vcpu_flush_pml_buffer
- Other refinement in coding style, comments description, etc.
Sanity test of live migration has been tested both with and without PML.
Kai Huang (10):
vmx: add new boot parameter to control PML enabl
It's possible domain has already been in log-dirty mode when creating vcpu, in
which case we should enable PML for this vcpu if PML has been enabled for the
domain.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmx.c | 23 +++
1 file changed, 23 insertions(+)
diff
A new 4K page pointer is added to arch_vmx_struct as PML buffer for vcpu. And a
new 'status' field is added to vmx_domain to indicate whether PML is enabled for
the domain or not.
Signed-off-by: Kai Huang
---
xen/include/asm-x86/hvm/vmx/vmcs.h | 8
1 file changed, 8 insertion
refore we introduce
paging_mark_gfn_dirty which is bulk of paging_mark_dirty but takes guest pfn as
parameter, and in flushing PML buffer we call paging_mark_gfn_dirty directly.
Original paging_mark_dirty then simply is a wrapper of paging_mark_gfn_dirty.
Signed-off-by: Kai Huang
---
xen/arch/
The patch adds PML definition and feature detection. Note PML won't be detected
if PML is disabled from boot parameter. PML is also disabled in construct_vmcs,
as it will only be enabled when domain is switched to log dirty mode.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/v
setting EPT entry to read-only, we just need
to clear D bit in order to log that GFN. For superpages, we still need to set it
to read-only as we need to split superpage to 4K pages in EPT violation.
Signed-off-by: Kai Huang
---
xen/arch/x86/mm/p2m-ept.c | 79
We need to flush PML buffer when it's full.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmx.c | 4
1 file changed, 4 insertions(+)
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index 6c4f78c..f11ac46 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arc
On 04/24/2015 03:30 PM, Jan Beulich wrote:
On 24.04.15 at 08:32, wrote:
On 04/17/2015 03:37 PM, Jan Beulich wrote:
On 17.04.15 at 09:23, wrote:
I see. I will do as you suggested:
ASSERT((v == current) || (!vcpu_runnable(v) && !v->is_running));
And v != current should be the only case req
On 04/17/2015 03:37 PM, Jan Beulich wrote:
On 17.04.15 at 09:23, wrote:
On 04/17/2015 02:58 PM, Jan Beulich wrote:
On 17.04.15 at 08:51, wrote:
On 04/17/2015 02:23 PM, Jan Beulich wrote:
On 17.04.15 at 05:10, wrote:
On 04/16/2015 11:42 PM, Jan Beulich wrote:
On 15.04.15 at 09:03, wrot
On 04/17/2015 10:31 AM, Kai Huang wrote:
On 04/17/2015 06:39 AM, Tian, Kevin wrote:
From: Kai Huang [mailto:kai.hu...@linux.intel.com]
Sent: Wednesday, April 15, 2015 3:04 PM
A new 4K page pointer is added to arch_vmx_struct as PML buffer for
vcpu.
And a
new 'status' field i
On Mon, Apr 20, 2015 at 4:29 PM, Tim Deegan wrote:
> At 17:29 +0800 on 17 Apr (1429291763), Kai Huang wrote:
>>
>>
>> On 04/17/2015 04:36 PM, Tim Deegan wrote:
>> > At 11:32 +0800 on 17 Apr (1429270332), Kai Huang wrote:
>> >>
>> >> On 04/17/
On 04/17/2015 04:36 PM, Tim Deegan wrote:
At 11:32 +0800 on 17 Apr (1429270332), Kai Huang wrote:
On 04/17/2015 08:10 AM, Tim Deegan wrote:
At 22:57 + on 16 Apr (1429225024), Tian, Kevin wrote:
From: Kai Huang [mailto:kai.hu...@linux.intel.com]
+if ( !p2m_change_type_one(v
On 04/17/2015 03:37 PM, Jan Beulich wrote:
On 17.04.15 at 09:23, wrote:
On 04/17/2015 02:58 PM, Jan Beulich wrote:
On 17.04.15 at 08:51, wrote:
On 04/17/2015 02:23 PM, Jan Beulich wrote:
On 17.04.15 at 05:10, wrote:
On 04/16/2015 11:42 PM, Jan Beulich wrote:
On 15.04.15 at 09:03, wrot
On 04/17/2015 02:58 PM, Jan Beulich wrote:
On 17.04.15 at 08:51, wrote:
On 04/17/2015 02:23 PM, Jan Beulich wrote:
On 17.04.15 at 05:10, wrote:
On 04/16/2015 11:42 PM, Jan Beulich wrote:
On 15.04.15 at 09:03, wrote:
+void vmx_vcpu_flush_pml_buffer(struct vcpu *v)
+{
+uint64_t *pml_b
On 04/17/2015 02:28 PM, Jan Beulich wrote:
On 17.04.15 at 04:40, wrote:
On 04/16/2015 11:54 PM, Jan Beulich wrote:
On 15.04.15 at 09:03, wrote:
This patch firstly enables EPT A/D bits if PML is used, as PML depends on
EPT
A/D bits to work. A bit is set for all present leaf p2m types, D b
On 04/17/2015 02:28 PM, Jan Beulich wrote:
On 17.04.15 at 04:46, wrote:
On 04/16/2015 11:51 PM, Jan Beulich wrote:
On 15.04.15 at 09:03, wrote:
@@ -190,9 +196,15 @@ static int hap_enable_log_dirty(struct domain *d, bool_t
log_global)
d->arch.paging.mode |= PG_log_dirty;
pagi
On 04/17/2015 02:23 PM, Jan Beulich wrote:
On 17.04.15 at 05:10, wrote:
On 04/16/2015 11:42 PM, Jan Beulich wrote:
On 15.04.15 at 09:03, wrote:
+void vmx_vcpu_flush_pml_buffer(struct vcpu *v)
+{
+uint64_t *pml_buf;
+unsigned long pml_idx;
+
+ASSERT(vmx_vcpu_pml_enabled(v));
+
+
On 04/17/2015 08:10 AM, Tim Deegan wrote:
At 22:57 + on 16 Apr (1429225024), Tian, Kevin wrote:
From: Kai Huang [mailto:kai.hu...@linux.intel.com]
+if ( !p2m_change_type_one(v->domain, gfn, p2m_ram_logdirty,
+p2m_ram_rw) )
+paging_mark_gfn_dirt
On 04/17/2015 06:57 AM, Tian, Kevin wrote:
From: Kai Huang [mailto:kai.hu...@linux.intel.com]
Sent: Wednesday, April 15, 2015 3:04 PM
This patch adds help functions to enable/disable PML, and flush PML buffer for
single vcpu and particular domain for further use.
Signed-off-by: Kai Huang
On 04/16/2015 11:42 PM, Jan Beulich wrote:
On 15.04.15 at 09:03, wrote:
+int vmx_vcpu_enable_pml(struct vcpu *v)
+{
+struct domain *d = v->domain;
+
+if ( vmx_vcpu_pml_enabled(v) )
+return 0;
+
+v->arch.hvm_vmx.pml_pg = d->arch.paging.alloc_page(d);
So you latch v->domain
On 04/16/2015 11:51 PM, Jan Beulich wrote:
On 15.04.15 at 09:03, wrote:
@@ -190,9 +196,15 @@ static int hap_enable_log_dirty(struct domain *d, bool_t
log_global)
d->arch.paging.mode |= PG_log_dirty;
paging_unlock(d);
+/* enable hardware-assisted log-dirty if it is supporte
On 04/17/2015 07:07 AM, Tian, Kevin wrote:
From: Jan Beulich [mailto:jbeul...@suse.com]
Sent: Thursday, April 16, 2015 11:52 PM
On 15.04.15 at 09:03, wrote:
@@ -190,9 +196,15 @@ static int hap_enable_log_dirty(struct domain *d,
bool_t log_global)
d->arch.paging.mode |= PG_log_dirty;
On 04/16/2015 11:54 PM, Jan Beulich wrote:
On 15.04.15 at 09:03, wrote:
This patch firstly enables EPT A/D bits if PML is used, as PML depends on EPT
A/D bits to work. A bit is set for all present leaf p2m types, D bit is set for
all writable types, except log-dirty type.
I think the tying o
On 04/17/2015 06:39 AM, Tian, Kevin wrote:
From: Kai Huang [mailto:kai.hu...@linux.intel.com]
Sent: Wednesday, April 15, 2015 3:04 PM
A new 4K page pointer is added to arch_vmx_struct as PML buffer for vcpu.
And a
new 'status' field is added to vmx_domain to indicate whether PML
On 04/17/2015 06:35 AM, Tian, Kevin wrote:
From: Kai Huang [mailto:kai.hu...@linux.intel.com]
Sent: Wednesday, April 15, 2015 3:04 PM
The patch adds PML definition and feature detection. Note PML won't be
detected
if PML is disabled from boot parameter. PML is also disabled in
construct
On 04/16/2015 11:33 PM, Jan Beulich wrote:
On 15.04.15 at 09:03, wrote:
--- a/xen/include/asm-x86/hvm/vmx/vmcs.h
+++ b/xen/include/asm-x86/hvm/vmx/vmcs.h
@@ -70,8 +70,12 @@ struct ept_data {
cpumask_var_t synced_mask;
};
+#define _VMX_DOMAIN_PML_ENABLED0
+#define VMX_DOMAIN_PM
Thanks Tim!
I'll send out the v3 addressing minor comments from Andrew and Jan
regarding to patch 1 & 2.
Thanks,
-Kai
On Thu, Apr 16, 2015 at 10:41 PM, Tim Deegan wrote:
> At 15:03 +0800 on 15 Apr (1429110222), Kai Huang wrote:
>> This v2 patch series was rebased on la
On 04/15/2015 06:15 PM, Andrew Cooper wrote:
On 15/04/15 08:03, Kai Huang wrote:
This patch adds doc description for new boot parameter 'ept=pml'.
Signed-off-by: Kai Huang
Personally, I would fold this patch into the previous so the
documentation is in the same patch as intr
On Wed, Apr 15, 2015 at 8:20 PM, Jan Beulich wrote:
On 15.04.15 at 09:03, wrote:
>> +static void __init parse_ept_param(char *s)
>> +{
>> +char *ss;
>> +int val;
>
> bool_t, and would better move ...
>
>> +
>> +do {
>> +val = !!strncmp(s, "no-", 3);
>
> ... here (making t
in order to log that GFN. For superpages, we still need to set it
to read-only as we need to split superpage to 4K pages in EPT violation.
Signed-off-by: Kai Huang
---
xen/arch/x86/mm/p2m-ept.c | 79 ++
xen/include/asm-x86/hvm/vmx/vmcs.h | 3 +-
xen
A top level EPT parameter "ept=" and a sub boolean "opt_pml_enabled"
are added to control PML. Other booleans can be further added for any other EPT
related features.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmcs.c | 31 +++
1 file ch
It's possible domain still remains in log-dirty mode when it is about to be
destroyed, in which case we should manually disable PML for it.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmx.c | 8
1 file changed, 8 insertions(+)
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen
It's possible domain has already been in log-dirty mode when creating vcpu, in
which case we should enable PML for this vcpu if PML has been enabled for the
domain.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmx.c | 23 +++
1 file changed, 23 insertions(+)
diff
nctions to enable/disable PML and flush PML
buffers. The new functions are named to be generic to cover potential futher
PML-like features for other platforms.
Signed-off-by: Kai Huang
---
xen/arch/x86/mm/hap/hap.c | 29 +
xen/arch/x86/mm/p2m.
This patch adds help functions to enable/disable PML, and flush PML buffer for
single vcpu and particular domain for further use.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmcs.c| 178 +
xen/include/asm-x86/hvm/vmx/vmcs.h | 9 ++
2 files
This patch adds doc description for new boot parameter 'ept=pml'.
Signed-off-by: Kai Huang
---
docs/misc/xen-command-line.markdown | 14 ++
1 file changed, 14 insertions(+)
diff --git a/docs/misc/xen-command-line.markdown
b/docs/misc/xen-command-line.markdown
ind
refore we introduce
paging_mark_gfn_dirty which is bulk of paging_mark_dirty but takes guest pfn as
parameter, and in flushing PML buffer we call paging_mark_gfn_dirty directly.
Original paging_mark_dirty then simply is a wrapper of paging_mark_gfn_dirty.
Signed-off-by: Kai Huang
---
xen/arch/
The patch adds PML definition and feature detection. Note PML won't be detected
if PML is disabled from boot parameter. PML is also disabled in construct_vmcs,
as it will only be enabled when domain is switched to log dirty mode.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/v
72811 80257 80139
72486 80413 81127
avg 72959 80718 81151
100%110.63% 111.22%
Kai Huang (11):
vmx: add new boot parameter to control PML enabling
doc: add description for new PML boot paramet
;t have to be initialized to zero explicitly as both
vcpu and domain structure are zero-ed when they are created.
Signed-off-by: Kai Huang
---
xen/include/asm-x86/hvm/vmx/vmcs.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/xen/include/asm-x86/hvm/vmx/vmcs.h
b/xen/include/asm-x86/hvm
We need to flush PML buffer when it's full.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmx.c | 4
1 file changed, 4 insertions(+)
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index 2ac1492..279e745 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arc
On 04/07/2015 05:24 PM, Tim Deegan wrote:
Hi,
At 16:30 +0800 on 07 Apr (1428424218), Kai Huang wrote:
Hi Jan, Tim, other maintainers,
Do you have comments? Or should I send out the v2 addressing Andrew's
comments, as it's been more than a week since this patch series were
sent
Hi Jan, Tim, other maintainers,
Do you have comments? Or should I send out the v2 addressing Andrew's
comments, as it's been more than a week since this patch series were
sent out?
Thanks,
-Kai
On 03/30/2015 01:50 PM, Kai Huang wrote:
On 03/28/2015 05:26 AM, Andrew Cooper wro
On Thu, Apr 2, 2015 at 5:58 PM, Andrew Cooper wrote:
> On 02/04/15 06:46, Kai Huang wrote:
>>
>>
>> On 03/28/2015 04:42 AM, Andrew Cooper wrote:
>>> On 27/03/15 02:35, Kai Huang wrote:
>>>> A top level EPT parameter "ept=" and a sub boolean
&g
On 03/28/2015 04:38 AM, Andrew Cooper wrote:
On 27/03/15 02:35, Kai Huang wrote:
PML requires A/D bit support so enable it for further use.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmcs.c| 1 +
xen/arch/x86/mm/p2m-ept.c | 8 +++-
xen/include/asm-x86/hvm/vmx
On 03/28/2015 04:42 AM, Andrew Cooper wrote:
On 27/03/15 02:35, Kai Huang wrote:
A top level EPT parameter "ept=" and a sub boolean "pml_enable" are
added to control PML. Other booleans can be further added for any other EPT
related features.
Signed-off-by: Kai Huang
Pl
On Mon, Mar 30, 2015 at 5:54 PM, Andrew Cooper
wrote:
> On 30/03/15 07:43, Kai Huang wrote:
>>
>>
>> On 03/28/2015 05:09 AM, Andrew Cooper wrote:
>>> On 27/03/15 02:35, Kai Huang wrote:
>>>
>>>> +}
>>>> +
>>>> +int vmx_vcp
On Mon, Mar 30, 2015 at 5:36 PM, Andrew Cooper
wrote:
> On 30/03/15 07:11, Kai Huang wrote:
>>
>>
>> On 03/28/2015 04:38 AM, Andrew Cooper wrote:
>>> On 27/03/15 02:35, Kai Huang wrote:
>>>> PML requires A/D bit support so enable it for furth
On 03/28/2015 05:12 AM, Andrew Cooper wrote:
On 27/03/15 02:35, Kai Huang wrote:
It's possible domain has already been in log-dirty mode when creating vcpu, in
which case we should enable PML for this vcpu if PML has been enabled for the
domain.
Signed-off-by: Kai Huang
---
xen/arc
On 03/28/2015 05:09 AM, Andrew Cooper wrote:
On 27/03/15 02:35, Kai Huang wrote:
This patch adds help functions to enable/disable PML, and flush PML buffer for
single vcpu and particular domain for further use.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmcs.c| 190
On 03/28/2015 04:48 AM, Andrew Cooper wrote:
On 27/03/15 02:35, Kai Huang wrote:
A new 4K page pointer is added to arch_vmx_struct as PML buffer for vcpu. And a
new 'status' field is added to vmx_domain to indicate whether PML is enabled for
the domain or not. The 'status
On 03/28/2015 04:46 AM, Andrew Cooper wrote:
On 27/03/15 02:35, Kai Huang wrote:
The patch adds PML definition and feature detection. Note PML won't be detected
if PML is disabled from boot parameter. PML is also disabled in construct_vmcs,
as it will only be enabled when domain is swi
On 03/28/2015 04:42 AM, Andrew Cooper wrote:
On 27/03/15 02:35, Kai Huang wrote:
A top level EPT parameter "ept=" and a sub boolean "pml_enable" are
added to control PML. Other booleans can be further added for any other EPT
related features.
Signed-off-by: Kai Huang
Pl
On 03/28/2015 04:38 AM, Andrew Cooper wrote:
On 27/03/15 02:35, Kai Huang wrote:
PML requires A/D bit support so enable it for further use.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmcs.c| 1 +
xen/arch/x86/mm/p2m-ept.c | 8 +++-
xen/include/asm-x86/hvm/vmx
On 03/28/2015 05:26 AM, Andrew Cooper wrote:
On 27/03/15 02:35, Kai Huang wrote:
Hi all,
This patch series adds PML support to Xen. Please kindly help to review it.
Overall this looks like a very good series, and it is particularly
helpful given the level of commenting.
Which platforms is
switching back to normal mode respectively.
Flushing PML buffer callback will be called from paging layer when flushing PML
buffer manually.
Signed-off-by: Kai Huang
---
xen/arch/x86/mm/hap/hap.c | 16 +++-
xen/arch/x86/mm/p2m.c | 36
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