Hi Julien,
On 02/02/2023 12:23, Julien Grall wrote:
>
>
> On 02/02/2023 11:12, Michal Orzel wrote:
>> Hi Julien,
>
> Hi Michal,
>
>>
>> On 02/02/2023 12:01, Julien Grall wrote:
>>>
>>>
>>> Hi Michal,
>>>
>>> On 0
panic message.
Signed-off-by: Michal Orzel
---
xen/arch/arm/domain_build.c | 23 ---
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index c2b97fa21e20..edca23b986d2 100644
--- a/xen/arch/arm
Hi Luca,
On 06/02/2023 15:31, Luca Fancellu wrote:
>
>
> Hi Xenia,
>
>> On 3 Feb 2023, at 19:09, Xenia Ragiadakou wrote:
>>
>> Signed-off-by: Xenia Ragiadakou
>> ---
>>
>> Changes in v3:
>> - the fixes are based solely to Eclair findings (the tool has been
>>adjusted to report only those
Replying to all,
On 21/10/2022 21:36, Stefano Stabellini wrote:
>
>
> On Fri, 21 Oct 2022, Andrew Cooper wrote:
>> On 21/10/2022 17:53, Michal Orzel wrote:
>>> Null scheduler is not enabled on non-debug Xen builds so the current
>>> test can lead to a failure on
Hi Stefano,
On 21/10/2022 23:42, Stefano Stabellini wrote:
>
>
> On Wed, 19 Oct 2022, Michal Orzel wrote:
>> At the moment, we define lots of test jobs in test.yaml, that make use
>> of the same configuration sections like variables, tags, artifacts.
>> Introduce t
Hello,
Recently I came across a deadcode in Xen Arm arch timer code. Briefly speaking,
we are routing
the NS phys timer (CNTP) IRQ to Xen, even though Xen does not make use of it
(as it uses the hypervisor timer CNTHP).
This timer is fully emulated, which means that there is nothing that can
tr
Make use of the macros defined in asm/pl011-uart.h instead of hardcoding
the values. Also, take the opportunity to fix the file extension in a
top-level comment.
No functional change intended.
Signed-off-by: Michal Orzel
---
xen/arch/arm/arm64/debug-pl011.inc | 20 +++-
1 file
Hi Julien,
On 24/10/2022 12:51, Julien Grall wrote:
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> On 24/10/2022 10:07, Michal Orzel wrote:
>> Hello,
>
> Hi Michal,
>
boot time cpupools
on arm64")
Signed-off-by: Michal Orzel
---
Changes in v2:
- was: automation: Do not use null scheduler for boot cpupools test
- modify the commit msg/title
- explicitly enable NULL scheduler by specifying all the required options
This patch acts as a prerequisite before m
attachments, clicking links, or responding.
>>>>
>>>>
>>>> On 24/10/2022 10:07, Michal Orzel wrote:
>>>>> Hello,
>>>>
>>>> Hi Michal,
>>>>
>>>>> Recently I came across a deadcode in Xen Arm arch timer code.
Hi Bertrand,
On 25/10/2022 09:45, Bertrand Marquis wrote:
>
>
> Hi Michal,
>
>> On 25 Oct 2022, at 08:11, Michal Orzel wrote:
>>
>> Hi,
>>
>> On 25/10/2022 03:29, Stefano Stabellini wrote:
>>>
>>>
>>> On Mon, 24 Oct 20
Hi Julien,
On 22/10/2022 17:04, Julien Grall wrote:
>
>
> From: Julien Grall
>
> In a follow-up patch, the base address for the common mappings will
> vary between arm32 and arm64. To avoid any duplication, define
> every mapping in the common region from the previous one.
Maybe the following
Hi Julien,
On 22/10/2022 17:04, Julien Grall wrote:
>
>
> From: Julien Grall
>
> At the moment, enable_mmu() will return to an address in the 1:1 mapping
> and each path are responsible to switch to the runtime mapping.
s/are/is/
>
> In a follow-up patch, the behavior to switch to the runtim
Hi Julien,
On 22/10/2022 17:04, Julien Grall wrote:
>
>
> From: Julien Grall
>
> The sequence for flushing the TLBs is 4 instruction long and often
> require an explanation how it works.
s/require/requires/
>
> So create an helper and use it in the boot code (switch_ttbr() is left
> alone fo
merged (the parent property overwrites the
child one).
Signed-off-by: Michal Orzel
---
Changes in v2:
- carve out anchors from extend jobs and use better naming
This patch is based on the CI next branch where we already have several
patches (already acked) to be merged into staging after the
Hi,
On 25/10/2022 12:31, Julien Grall wrote:
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> On 25/10/2022 10:21, Michal Orzel wrote:
>> Hi Julien,
>
> Hi Michal,
&
Hi all,
On 25/10/2022 10:20, Bertrand Marquis wrote:
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> Hi Michal,
>
>> On 25 Oct 2022, at 09:07, Michal Orzel wrote:
>>
Hi,
On 26/10/2022 17:30, Stefano Stabellini wrote:
>
>
> On Wed, 26 Oct 2022, Bertrand Marquis wrote:
>>> On 26 Oct 2022, at 12:29, Michal Orzel wrote:
>>>
>>> Hi all,
>>>
>>> On 25/10/2022 10:20, Bertrand Marquis wrote:
>>>> Ca
Hi Rahul,
On 26/10/2022 16:33, Rahul Singh wrote:
>
>
> Hi Julien,
>
>> On 26 Oct 2022, at 2:36 pm, Julien Grall wrote:
>>
>>
>>
>> On 26/10/2022 14:17, Rahul Singh wrote:
>>> Hi All,
>>
>> Hi Rahul,
>>
>>> At Arm, we started to implement the POC to support 2 levels of page
>>> tables/nested
Hi Rahul,
On 27/10/2022 18:33, Julien Grall wrote:
>
>
> On 27/10/2022 17:08, Rahul Singh wrote:
>> Hi Julien,
>
> Hi Rahul,
>
>>> On 26 Oct 2022, at 8:48 pm, Julien Grall wrote:
>>>
>>>
>>>
>>> On 26/10/2022 15:33, Rahul Singh wrote:
Hi Julien,
>>>
>>> Hi Rahul,
>>>
> On 26 Oct 2022
well as the
code within the handler. Since timer_interrupt handler is now only used
by the CNTHP, remove the IRQ affiliation condition. Keep the calls to
zero the CNTP_CTL_EL0 register on timer init/deinit for sanity and also remove
the corresponding perf counter definition.
Signed-off-by: Michal
Hi Julien,
On 28/10/2022 11:03, Julien Grall wrote:
>
>
> Hi Michal,
>
> On 28/10/2022 08:56, Michal Orzel wrote:
>> At the moment, we route NS phys timer IRQ to Xen even though it does not
>> make use of this timer. Xen uses hypervisor timer for itself and the
readability by adding new lines \btw code and comments.
Keep the calls to zero the CNTP_CTL_EL0 register for sanity and also
remove the corresponding perf counter definition.
Signed-off-by: Michal Orzel
---
Changes in v2:
- take the opportunity to rename the handler, modify the condition to
avoid the
On 28/10/2022 17:45, Bertrand Marquis wrote:
>
>
> Hi Julien,
>
>> On 28 Oct 2022, at 16:01, Julien Grall wrote:
>>
>>
>>
>> On 28/10/2022 15:37, Bertrand Marquis wrote:
>>> Hi Julien,
>>
>> Hi Bertrand,
>>
On 28 Oct 2022, at 14:27, Julien Grall wrote:
On 28/10/2022
Hi Bertrand,
On 31/10/2022 15:00, Bertrand Marquis wrote:
>
>
> This patch series is a first attempt to check if we could use Yocto in
> gitlab ci to build and run xen on qemu for arm, arm64 and x86.
>
> The first patch is creating a container with all elements required to
> build Yocto, a chec
Hi Ayan,
On 31/10/2022 16:13, Ayan Kumar Halder wrote:
>
>
> Refer ARM DDI 0487G.b ID072021, EC==0b011000 is supported for Aarch64 state
I think when adding new code we should be taking the latest spec (which is I.a)
as a base +
you are lacking the information \wrt page number, table, whatever
Hi Ayan,
On 31/10/2022 16:13, Ayan Kumar Halder wrote:
>
>
> Refer https://elixir.bootlin.com/linux/v6.1-rc1/source/arch/arm64/ \
You should not split the link as it is becoming unusable in that form.
> include/asm/cputype.h#L14 , for the macros specific for arm64.
>
> Refer https://elixir.boo
On 31/10/2022 18:53, Michal Orzel wrote:
>
>
> Hi Ayan,
>
> On 31/10/2022 16:13, Ayan Kumar Halder wrote:
>>
>>
>> Refer
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Felixir.bootlin.com%2Flinux%2Fv6.1-rc1%2Fsource%2Farch
Hi Ayan,
On 31/10/2022 16:13, Ayan Kumar Halder wrote:
>
>
> In some situations (eg GICR_TYPER), the hypervior may need to emulate
> 64bit registers in aarch32 mode. In such situations, the hypervisor may
> need to read/modify the lower or upper 32 bits of the 64 bit register.
>
> In aarch32, '
L)
> #define GICR_PENDBASER_RES0_MASK \
> -(BIT(63, UL) | GENMASK(61, 59) | GENMASK(55, 52) | \
> - GENMASK(15, 12) | GENMASK(6, 0))
> + (BIT(63, ULL) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \
It would be good to align \ but at the same time I can understand that it was
not
aligned before your change and you may not want to do this, so:
Reviewed-by: Michal Orzel
~Michal
that has no prototype.
Apart from that:
Reviewed-by: Michal Orzel
~Michal
Hi Ayan,
On 31/10/2022 16:13, Ayan Kumar Halder wrote:
>
>
> Refer "Arm IHI 0069H ID020922", 12.4.6, Interrupt Controller List Registers
>
> AArch64 System register ICH_LR_EL2 bits [31:0] are architecturally
> mapped to AArch32 System register ICH_LR[31:0].
> AArch64 System register ICH_LR_EL2
forming atomic operations.
>
> Signed-off-by: Ayan Kumar Halder
Reviewed-by: Michal Orzel
> +#define ICH_AP1R2_EL2 __AP1Rx_EL2(2)
> +#define ICH_AP1R3_EL2 __AP1Rx_EL2(3)
This might need to be re-aligned after you fix patch no. 7.
Then, you can add:
Reviewed-by: Michal Orzel
~Michal
Hi Ayan,
On 31/10/2022 16:13, Ayan Kumar Halder wrote:
>
The title is a bit ambiguous given that the previous patches were also defining
GIC registers.
Maybe adding "remaining" would result in a better commit title.
>
> Refer "Arm IHI 0069H ID020922"
> 12.5.23 ICC_SGI1R, Interrupt Controller S
Hi Ayan,
On 03/11/2022 21:14, Ayan Kumar Halder wrote:
>
> On 03/11/2022 15:08, Michal Orzel wrote:
>> Hi Ayan,
> Hi Michal,
>>
>> On 31/10/2022 16:13, Ayan Kumar Halder wrote:
>> The title is a bit ambiguous given that the previous patches were also
>>
Hi Ayan,
On 31/10/2022 16:13, Ayan Kumar Halder wrote:
>
>
> Refer ARM DDI 0487G.b ID072021,
> D13.2.86 -
> ID_PFR1_EL1, AArch32 Processor Feature Register 1
>
> GIC, bits[31:28] == 0b0001 for GIC3.0 on Aarch32
>
> One can now enable GICv3 on AArch32 systems. However, ITS is not supported.
> T
On 04/11/2022 12:30, Julien Grall wrote:
>
>
>
>
>
> On Fri, 4 Nov 2022 at 12:09, Ayan Kumar Halder <mailto:ayank...@amd.com>> wrote:
>
>
> On 04/11/2022 09:55, Michal Orzel wrote:
> > Hi Ayan,
> Hi Michal,
> >
&
Hi Bertrand and Stefano,
On 31/10/2022 16:00, Bertrand Marquis wrote:
>
>
> Hi Michal,
>
>> On 31 Oct 2022, at 14:39, Michal Orzel wrote:
>>
>> Hi Bertrand,
>>
>> On 31/10/2022 15:00, Bertrand Marquis wrote:
>>>
>>>
>>> T
use this explained why we
> can't check in production. So how about the following commit message:
>
> "
> xen/arm: Enforce alignment check in debug build for {read, write}_atomic
>
> Xen provides helper to atomically read/write memory (see {read,
> write}_atomic()). Those
Hi Bertrand,
On 08/11/2022 09:42, Bertrand Marquis wrote:
>
>
> Hi Michal,
>
>> On 7 Nov 2022, at 07:50, Michal Orzel wrote:
>>
>> Hi Bertrand and Stefano,
>>
>> On 31/10/2022 16:00, Bertrand Marquis wrote:
>>>
>>>
>>&
Hi Jiamei,
On 09/11/2022 08:20, Jiamei Xie wrote:
>
>
> Hi all,
>
> When the guest kernel enables DMA engine with "CONFIG_DMA_ENGINE=y", Linux
> AMBA PL011 driver will access PL011 DMACR register. But this register have
> not been supported by vpl011 of Xen. Xen will inject a data abort into
ed.
If Linux tries to write to some of the none-spec compliant registers - it is
its fault.
> Best wishes
> Jiamei Xie
>
~Michal
>
>
>> -Original Message-
>> From: Michal Orzel
>> Sent: Wednesday, November 9, 2022 3:40 PM
>> To: Jiamei Xie ; xen-
Hi Stefano,
On 10/11/2022 01:18, Stefano Stabellini wrote:
>
>
> On Mon, 7 Nov 2022, Michal Orzel wrote:
>> Hi Bertrand and Stefano,
>>
>> On 31/10/2022 16:00, Bertrand Marquis wrote:
>>>
>>>
>>> Hi Michal,
>>>
>>&g
Hello,
On 10/11/2022 11:08, Bertrand Marquis wrote:
>
>
> Hi Michal,
>
>> On 10 Nov 2022, at 07:34, Michal Orzel wrote:
>>
>> Hi Stefano,
>>
>> On 10/11/2022 01:18, Stefano Stabellini wrote:
>>>
>>>
>>> On Mon, 7 Nov 2022,
Hi Julien,
On 16/11/2022 00:10, Julien Grall wrote:
>
>
> Hi Michal,
>
> On 24/10/2022 11:05, Michal Orzel wrote:
>> Make use of the macros defined in asm/pl011-uart.h instead of hardcoding
>> the values. Also, take the opportunity to fix the file extension in a
>
Xen commit 942ac5fc15ec ("xen/arm, device-tree: Make static-mem
use #{address,size}-cells") dropped these custom properties in favor of
reusing regular #{address/size}-cells from the chosen node for the
xen,static-mem property. Reflect this change in ImageBuilder.
Signed-off-by: Mi
Add a file with a table listing files in the Xen codebase that originated
from external sources (e.g. Linux kernel). This is done in order to
improve traceability, help with the review process and act as a base for
listing files to exclude from MISRA checkers.
Signed-off-by: Michal Orzel
Hi Julien,
On 16/11/2022 14:41, Julien Grall wrote:
>
>
> On 16/11/2022 08:05, Michal Orzel wrote:
>> On 16/11/2022 00:10, Julien Grall wrote:
>>>
>>>
>>> Hi Michal,
>>>
>>> On 24/10/2022 11:05, Michal Orzel wrote:
>>>>
Hi Julien,
On 16/11/2022 16:56, Julien Grall wrote:
>
>
> On 16/11/2022 14:45, Michal Orzel wrote:
>> Hi Julien,
>
> Hi Michal,
>
>>>
>>>> and use it in the pl011-debug files (+ there is a question whether we
>>>> should define WLEN_7
Hi Julien,
On 16/11/2022 19:37, Julien Grall wrote:
>
>
> Hi Michal,
>
> On 16/11/2022 18:05, Michal Orzel wrote:
>> On 16/11/2022 16:56, Julien Grall wrote:
>>>
>>>
>>> On 16/11/2022 14:45, Michal Orzel wrote:
>>>> Hi Julien,
>&
Hi Julien,
On 17/11/2022 10:29, Julien Grall wrote:
>
>
> On 17/11/2022 08:34, Michal Orzel wrote:
>> Hi Julien,
>>
>> On 16/11/2022 19:37, Julien Grall wrote:
>>>
>>>
>>> Hi Michal,
>>>
>>> On 16/11/2022
Hi Jan,
Thanks for looking at it.
On 17/11/2022 11:03, Jan Beulich wrote:
>
>
> On 16.11.2022 10:20, Michal Orzel wrote:
>> --- /dev/null
>> +++ b/docs/misra/external-files.txt
>> @@ -0,0 +1,70 @@
>> +External files in Xen
>> +=
&
On 17/11/2022 10:53, Michal Orzel wrote:
>
>
> Hi Julien,
>
> On 17/11/2022 10:29, Julien Grall wrote:
>>
>>
>> On 17/11/2022 08:34, Michal Orzel wrote:
>>> Hi Julien,
>>>
>>> On 16/11/2022 19:37, Julien Grall wrote:
>>>>
Hi Ayan,
On 11/11/2022 15:17, Ayan Kumar Halder wrote:
> Sysreg emulation is 64-bit specific, so guard the calls to
> vgic_v3_emulate_sysreg() as well as the function itself with
> "#ifdef CONFIG_ARM_64".
>
> Signed-off-by: Ayan Kumar Halder
Reviewed-by: Michal Orzel
~Michal
fore fold vreg_reg_* helper in the size specific one and use the
> appropriate type based on the size requested.
>
> Signed-off-by: Ayan Kumar Halder
Reviewed-by: Michal Orzel
~Michal
ess to affinity level 3 needs to be guarded within
> "ifdef CONFIG_ARM_64".
>
> Signed-off-by: Ayan Kumar Halder
Reviewed-by: Michal Orzel
although, IMO the commit msg does not reflect the change (i.e. you do nothing
related to accessing MPIDR, but instead you are just not
aff3 have been contained within "#ifdef CONFIG_ARM_64".
s/have been contained within/has been protected with/
> Also, v->arch.vmpidr is a 32 bit register on AArch32. So, we have copied it to
s/copied/assigned/
> 'uint64_t vmpidr' to perform the shifts.
>
>
remove installation of these packages from the
test scripts. This is done in order not to break the CI in-between.
Signed-off-by: Michal Orzel
---
automation/build/debian/stretch.dockerfile | 3 +++
automation/build/debian/unstable-arm64v8.dockerfile | 7 +++
2 files changed, 10 inse
This patch series moves the installation of packages at runtime from the test
scripts into the respective containers.
This series is based on the CI next branch:
https://gitlab.com/xen-project/people/sstabellini/xen/-/tree/next
Michal Orzel (2):
automation: Install packages required by tests
Now, when these packages are already installed in the respective
containers, we can remove them from the test scripts.
Signed-off-by: Michal Orzel
---
automation/scripts/qemu-alpine-x86_64.sh| 4
automation/scripts/qemu-smoke-dom0-arm32.sh | 8
automation/scripts/qemu
Hi Jiamei,
On 18/11/2022 03:18, Jiamei Xie wrote:
>
>
> Hi
>
> Sorry there is no subject in the last email. So add in this one.
I would consider re-pushing this patch(although please wait for some comments).
The reason being, a patch without a subject is not picked by patchwork/b4 or
other
to
Hi Jimaei,
On 18/11/2022 03:00, Jiamei Xie wrote:
>
>
> Date: Thu, 17 Nov 2022 11:07:12 +0800
> Subject: [PATCH] xen/arm: vpl011: Make access to DMACR write-ignore
>
> When the guest kernel enables DMA engine with "CONFIG_DMA_ENGINE=y",
> Linux SBSA PL011 driver will access PL011 DMACR register
Hi Bertrand,
Just, some minor comments.
On 17/11/2022 10:39, Bertrand Marquis wrote:
>
>
> Add containers suitable to run yocto kirkstone build based on ubuntu
> 22.04. It contains all packages required by Yocto and a checkout of the
> layers required to build Xen with Yocto.
>
> Add a generic
Hi Bertrand,
On 17/11/2022 10:39, Bertrand Marquis wrote:
>
>
> Add make clean support to remove the containers from the local docker
> registry:
I have to say that I am a bit scared of adding a clean rule.
make clean is something that can easily sneak into this directory and can
remove the yoct
Hi Ayan,
On 11/11/2022 15:17, Ayan Kumar Halder wrote:
> Refer "Arm IHI 0069H ID020922", 12.4.6, Interrupt Controller List Registers
>
> AArch64 System register ICH_LR_EL2 bits [31:0] are architecturally
> mapped to AArch32 System register ICH_LR[31:0].
> AArch64 System register ICH_LR_EL2 bits [
Hi Julien,
On 18/11/2022 10:58, Julien Grall wrote:
>
>
> On 17/11/2022 12:52, Michal Orzel wrote:
>>
>>
>> On 17/11/2022 10:53, Michal Orzel wrote:
>>>
>>>
>>> Hi Julien,
>>>
>>> On 17/11/2022 10:29, Julien Grall wrote:
early_uart_init macro is only used if CONFIG_EARLY_UART_INIT is set.
This config option depends on EARLY_UART_PL011, so there is no point
in defining it for MESON, especially if it is empty. Remove it and adapt
the existing comment.
Signed-off-by: Michal Orzel
---
xen/arch/arm/arm64/debug
Some time ago, Linux switched the format of docs to ReST and the format
of device-tree bindings to json-schema.
Signed-off-by: Michal Orzel
---
docs/misc/arm/booting.txt | 8
docs/misc/arm/passthrough.txt | 8
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a
Make use of the macros defined in asm/pl011-uart.h instead of hardcoding
the values. Also, take the opportunity to fix the file extension in a
top-level comment.
No functional change intended.
Signed-off-by: Michal Orzel
Reviewed-by: Luca Fancellu
Acked-by: Julien Grall
---
This patch has
This patch series performs simple early printk code cleanup around PL011.
No functional changes has been made.
Michal Orzel (3):
xen/arm: Drop early_uart_init macro from debug-meson.inc
xen/arm: debug-pl011.inc: Use macros instead of hardcoded values
xen/arm: Define WLEN_8 macro and use it
At the moment, early printk code for pl011 uses a hardcoded value
for 8n1 LCR configuration. Define and use macro WLEN_8 for that purpose
(no parity and 1 stop bit are defined as 0).
Signed-off-by: Michal Orzel
---
xen/arch/arm/arm32/debug-pl011.inc| 2 +-
xen/arch/arm/arm64/debug-pl011.inc
Hi Bertrand,
On 18/11/2022 12:44, Bertrand Marquis wrote:
>
>
> Hi Michal,
>
>> On 18 Nov 2022, at 08:53, Michal Orzel wrote:
>>
>> Hi Bertrand,
>>
>> Just, some minor comments.
>>
>> On 17/11/2022 10:39, Bertrand Marquis wrote:
>>&g
Hi Ayan,
On 11/11/2022 15:17, Ayan Kumar Halder wrote:
> Adapt save_aprn_regs()/restore_aprn_regs() for AArch32.
>
> For which we have defined the following registers:-
> 1. Interrupt Controller Hyp Active Priorities Group0 Registers 0-3
> 2. Interrupt Controller Hyp Active Priorities Group1 Regi
Hi Ayan,
On 11/11/2022 15:17, Ayan Kumar Halder wrote:
> Define missing assembly aliases for GIC registers on arm32, taking the ones
> defined already for arm64 as a base. Aliases are defined according to the
> GIC Architecture Specification ARM IHI 0069H.
>
> Defined the following registers:-
>
Hi Ayan,
On 11/11/2022 15:17, Ayan Kumar Halder wrote:
> "unsigned long long" is defined as 64 bits on AArch64 and AArch32
> Thus, one should this instead of "unsigned long" which is 32 bits
> on AArch32.
>
> Also use 'PRIx64' instead of 'lx' or 'llx' to print uint64_t.
>
> Signed-off-by: Ayan K
Hi,
On 22/11/2022 13:25, Julien Grall wrote:
>
>
> Hi,
>
> On 22/11/2022 05:46, Jiamei Xie wrote:
>> When the guest kernel enables DMA engine with "CONFIG_DMA_ENGINE=y",
>> Linux SBSA PL011 driver will access PL011 DMACR register in some
>> functions. As chapter "B Generic UART" in "ARM Server
Hi Julien,
On 22/11/2022 21:31, Julien Grall wrote:
>
>
> On 17/11/2022 13:39, Michal Orzel wrote:
>> Hi Ayan,
>>
>> On 11/11/2022 15:17, Ayan Kumar Halder wrote:
>>> Refer ARM DDI 0487I.a ID081822, G8-9817, G8.2.169
>>> Affinity level 3 is no
t Controller (GIC) implemented with an Armv8-R PE must not
> implement LPI support."
>
> By default GICv3 is disabled on AArch32 and enabled on AArch64.
>
> Updated SUPPORT.md to state that GICv3 on Arm32 is not security supported.
>
> Signed-off-by: Ayan Kumar Halder
Hi Henry,
On 23/11/2022 05:03, Henry Wang wrote:
>
>
> Signed-off-by: Henry Wang
> ---
> v3 -> v4:
> - Use the corrected sentence for VIRT_SSBD and MSR_SPEC_CTRL
> - Clarify that the virtio-mmio toolstack for ARM is only creating the
> device-tree binding.
> - Remove the "initial" in i.MX ent
Hi Henry,
On 23/11/2022 11:46, Henry Wang wrote:
>
>
> Hi Michal,
>
>> -Original Message-
>> Subject: Re: [PATCH v4 1/3] CHANGELOG: Add missing entries for work during
>> the 4.17 release
>> Hi Henry,
>> Looking at the "Added" section for the previous releases, we seem to
>> mention the
, because less than zero comparison of an unsigned value
can never be true. Fix it by defining vpl011_virq as int.
Fixes: 3580c8b2dfc3 ("xen/arm: if direct-map domain use native UART address and
IRQ number for vPL011")
Signed-off-by: Michal Orzel
---
To be considered to be taken for 4.17
L2) << 32) | ICH_LR<0...15>_EL2
>
> Also, ICR_LR macros need to be modified as ULL is 64 bits for AArch32 and
> AArch64.
>
> Signed-off-by: Ayan Kumar Halder
Reviewed-by: Michal Orzel ,
with two remarks (this is up to maintainers as these are rather cosmetic
changes).
iorities Group1 Registers 0-3
>
> Signed-off-by: Ayan Kumar Halder
Reviewed-by: Michal Orzel
~Michal
egister
> 11. Interrupt Controller Empty List Register Status Register
> 12. Interrupt Controller Virtual Machine Control Register
>
> Signed-off-by: Ayan Kumar Halder
Reviewed-by: Michal Orzel
with one remark...
> ---
>
> Changes from :-
> v1 - 1. Moved coproc regs defin
t Controller (GIC) implemented with an Armv8-R PE must not
> implement LPI support."
>
> By default GICv3 is disabled on AArch32 and enabled on AArch64.
>
> Updated SUPPORT.md to state that GICv3 on Arm32 is not security supported.
>
> Signed-off-by: Ayan Kumar Halder
Reviewed-by: Michal Orzel
~Michal
Hi Bertrand,
On 30/11/2022 13:15, Bertrand Marquis wrote:
>
>
> From: Michal Orzel
>
> Populate test jobs for Yocto based tests using the provided containers.
> Due to the size restrictions, it is currently not possible to split the
> build and run tasks, therefore ev
ge
>
> Signed-off-by: Bertrand Marquis
Reviewed-by: Michal Orzel
~Michal
Hi Bertrand,
I will try to build and run the yocto containers for a test.
In the meantime I just spotted one thing.
On 30/11/2022 13:15, Bertrand Marquis wrote:
>
>
> Add containers suitable to run yocto kirkstone build based on ubuntu
> 22.04. It contains all packages required by Yocto and a c
Hi Bertrand,
On 30/11/2022 16:07, Bertrand Marquis wrote:
>
>
> Hi Michal,
>
>> On 30 Nov 2022, at 13:02, Michal Orzel wrote:
>>
>> Hi Bertrand,
>>
>> On 30/11/2022 13:15, Bertrand Marquis wrote:
>>>
>>>
>>> From: Mic
n improvement.
>
> [1] https://developer.arm.com/documentation/den0094/c/?lang=en
> [2]
> https://lore.kernel.org/xen-devel/alpine.DEB.2.22.394.2211161552420.4020@ubuntu-linux-20-04-desktop/
>
> Signed-off-by: Jiamei Xie
The patch looks good, so:
Reviewed-by: Michal Orze
On 01/12/2022 09:42, Michal Orzel wrote:
>
>
> Hi Jiamei,
>
> On 01/12/2022 09:03, Jiamei Xie wrote:
>>
>>
>> When the guest kernel enables DMA engine with "CONFIG_DMA_ENGINE=y",
>> Linux SBSA PL011 driver will access PL011 DMACR register in
Hi Julien,
On 01/12/2022 09:52, Julien Grall wrote:
>
>
> Hi,
>
> On 01/12/2022 09:42, Michal Orzel wrote:
>> On 01/12/2022 09:03, Jiamei Xie wrote:
>>>
>>>
>>> When the guest kernel enables DMA engine with "CONFIG_DMA_ENGINE=y",
>&
Hi Rahul,
On 01/12/2022 17:02, Rahul Singh wrote:
>
>
> The SMMUv3 supports two stages of translation. Each stage of translation can
> be
> independently enabled. An incoming address is logically translated from VA to
> IPA in stage 1, then the IPA is input to stage 2 which translates the IPA t
ge
>
> Signed-off-by: Bertrand Marquis
Reviewed-by: Michal Orzel
~Michal
as those files are
> generated.
>
> Signed-off-by: Bertrand Marquis
Reviewed-by: Michal Orzel
I know that Stefano tested the build/run on arm64. I did the same locally
on x86 successfully.
~Michal
Hi Rahul,
On 01/12/2022 17:02, Rahul Singh wrote:
>
>
> XEN will create an Emulated SMMUv3 device tree node in the device tree
> to enable the dom0less domains to discover the virtual SMMUv3 during
> boot. Emulated SMMUv3 device tree node will only be created when cmdline
> option vsmmuv3 is ena
Hi Rahul,
On 01/12/2022 17:02, Rahul Singh wrote:
>
>
> To configure IOMMU in guest for passthrough devices, user will need to
> copy the unmodified "iommus" property from host device tree to partial
> device tree. To enable the dom0 linux kernel to confiure the IOMMU
> correctly replace the pha
Hi Rahul,
On 01/12/2022 17:02, Rahul Singh wrote:
>
>
> This patch adds basic framework for vIOMMU.
>
> Signed-off-by: Rahul Singh
> ---
> xen/arch/arm/domain.c| 17 +++
> xen/arch/arm/domain_build.c | 3 ++
> xen/arch/arm/include/asm/viommu.h| 70 +++
Hi Rahul,
On 01/12/2022 17:02, Rahul Singh wrote:
>
>
> domain_viommu_init() will be called during domain creation and will add
> the dummy trap handler for virtual IOMMUs for guests.
>
> A host IOMMU list will be created when host IOMMU devices are probed
> and this list will be used to create
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