From: Abhishek Paliwal abhishek.pali...@aricent.com
From: David Daney david.da...@cavium.com
Combined several changes:
Add workaround for chips with broken irqs.
Use High Level Controller when possible.
Retry more situations where arbitration is lost.
Clean up resource allocation code.
From: Abhishek Paliwal abhishek.pali...@aricent.com
From: David Daney david.da...@cavium.com
... to allow interaction with cvmx-twsi code.
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Abhishek Paliwal abhishek.pali...@aricent.com
---
arch/mips/include/asm/octeon/octeon.h |
From: Abhishek Paliwal abhishek.pali...@aricent.com
From: David Daney david.da...@cavium.com
The addresses of the GPIO_BIT_CFG registers have a different layout on
cn78XX.
Define OF_GPIO_OPEN_DRAIN flag for Open Drain outputs.
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by:
From: Abhishek Paliwal abhishek.pali...@aricent.com
From: David Daney david.da...@cavium.com
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Abhishek Paliwal abhishek.pali...@aricent.com
---
arch/mips/cavium-octeon/Makefile| 1 +
From: Abhishek Paliwal abhishek.pali...@aricent.com
From: David Daney david.da...@cavium.com
... in order to keep all SMP related code together.
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Abhishek Paliwal abhishek.pali...@aricent.com
---
arch/mips/cavium-octeon/setup.c
From: Abhishek Paliwal abhishek.pali...@aricent.com
From: Aaron Williams aaron.willi...@cavium.com
Currently there is no easy way to map a device tree node to a memory
accessor function for devices like I2C EEPROMs. For example, the Vitesse
vsc848x 10G PHY driver needs to be able to use the I2C
From: Abhishek Paliwal abhishek.pali...@aricent.com
From: Aaron Williams aaron.willi...@cavium.com
The at24 module will now register its memory accessor functions with its
device tree entry so that other modules may call these functions based on
the device tree node.
Signed-off-by: Aaron
From: Abhishek Paliwal abhishek.pali...@aricent.com
From: David Daney david.da...@cavium.com
cn78XX has a different interrupt architecture, so we have to manage the
interrupts a little differently.
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Abhishek Paliwal
system.
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Leonid Rosenboim lrosenb...@caviumnetworks.com
Signed-off-by: Chandrakala Chavva ccha...@caviumnetworks.com
Signed-off-by: Abhishek Paliwal abhishek.pali...@aricent.com
---
arch/mips/cavium-octeon/setup.c | 12 ++-
arch
david.da...@cavium.com
Signed-off-by: Leonid Rosenboim lrosenb...@caviumnetworks.com
Signed-off-by: Chandrakala Chavva ccha...@caviumnetworks.com
Signed-off-by: Abhishek Paliwal abhishek.pali...@aricent.com
---
arch/mips/kernel/genex.S | 20
1 file changed, 20 insertions
From: Abhishek Paliwal abhishek.pali...@aricent.com
From: Prem Mallappa pmalla...@caviumnetworks.com
From: David Daney david.da...@cavium.com
Signed-off-by: Prem Mallappa pmalla...@caviumnetworks.com
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Abhishek Paliwal
From: Abhishek Paliwal abhishek.pali...@aricent.com
From: Chandrakala Chavva ccha...@caviumnetworks.com
Add missing error interrupt, nxm_wr_err, write to no-existent memory.
MIPS/EDAC: Set error reporting state to polling
For LMC controller set error reporting state to EDAC_OPSTATE_POLL
From: Abhishek Paliwal abhishek.pali...@aricent.com
From: David Daney david.da...@cavium.com
From: Leonid Rosenboim lrosenb...@caviumnetworks.com
From: Chandrakala Chavva ccha...@caviumnetworks.com
MIPS: OCTEON: Force L1 Dcache and TLB parity errors for testing.
MIPS: OCTEON: Keep reset value
From: Abhishek Paliwal abhishek.pali...@aricent.com
From: David Daney david.da...@cavium.com
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Abhishek Paliwal abhishek.pali...@aricent.com
---
arch/mips/cavium-octeon/dma-octeon.c | 3 ++-
1 file changed, 2 insertions(+), 1
From: Abhishek Paliwal abhishek.pali...@aricent.com
From: Chandrakala Chavva ccha...@caviumnetworks.com
Use correct CSR for checking Double/Single bit ECC errors for various types.
Signed-off-by: Chandrakala Chavva ccha...@caviumnetworks.com
Signed-off-by: Abhishek Paliwal abhishek.pali
From: Abhishek Paliwal abhishek.pali...@aricent.com
From: David Daney dda...@caviumnetworks.com
MIPS: Add Octeon2 optimizations to clear_page.
Use the ZCBT instruction for Octeon2.
Reduce the number of generated instructions when possible.
Both OCTEON3 and OCTEON2 use the same instrucitons for
From: Abhishek Paliwal abhishek.pali...@aricent.com
From: Chandrakala Chavva ccha...@caviumnetworks.com
FAM_* macros are replaced with OCTEON_IS_OCTEON* macros.
Signed-off-by: Chandrakala Chavva ccha...@caviumnetworks.com
Signed-off-by: Abhishek Paliwal abhishek.pali...@aricent.com
---
drivers
From: Abhishek Paliwal abhishek.pali...@aricent.com
From: Prem Mallappa pmalla...@caviumnetworks.com
From: David Daney david.da...@cavium.com
Add check to see if DDR is available.
Signed-off-by: Prem Mallappa pmalla...@caviumnetworks.com
Signed-off-by: David Daney david.da...@cavium.com
From: Abhishek Paliwal abhishek.pali...@aricent.com
Update EDAC L2C and LMC driver support for Octeon3.
Added new Error injector module to verify L2C and various other error
conditions.
Updated clearing of page in linux kernel by using ZCB instructions, new
instruction added in Octeon2 and
From: Abhishek Paliwal abhishek.pali...@aricent.com
From: David Daney dda...@caviumnetworks.com
These instructions are available in OCTEON II CPUs.
Signed-off-by: David Daney dda...@caviumnetworks.com
Signed-off-by: Leonid Rosenboim lrosenb...@caviumnetworks.com
Signed-off-by: Abhishek Paliwal
From: Abhishek Paliwal abhishek.pali...@aricent.com
From: Andreas Herrmann andreas.herrm...@caviumnetworks.com
commit cd3f5389489146297eb2c11e4f9d1c4e8aaeb59f upstream
Otherwise __builtin_unreachable might be called.
Signed-off-by: Andreas Herrmann andreas.herrm...@caviumnetworks.com
Cc:
From: Abhishek Paliwal abhishek.pali...@aricent.com
From: David Daney david.da...@cavium.com
commit a36d8225bceba4b7be47ade34d175945f85cffbc upstream
Some versions of the assembler will not assemble CFC1 for OCTEON, so override
the ISA for these.
Add r4k_fpu.o to handle low level FPU
From: Abhishek Paliwal abhishek.pali...@aricent.com
From: David Daney david.da...@cavium.com
Some versions of the assembler will not assemble CFC1 for OCTEON, so
override the ISA for these.
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Abhishek Paliwal
From: Abhishek Paliwal abhishek.pali...@aricent.com
From: Chandrakala Chavva ccha...@caviumnetworks.com
Read clock rate from the correct CSR. Don't clear COP0_DCACHE for OCTEONIII.
Signed-off-by: Chandrakala Chavva ccha...@caviumnetworks.com
Signed-off-by: Abhishek Paliwal abhishek.pali
From: Abhishek Paliwal abhishek.pali...@aricent.com
From: David Daney david.da...@cavium.com
Disable ICache prefetch for certian Octeon II processors.
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Abhishek Paliwal abhishek.pali...@aricent.com
---
From: Abhishek Paliwal abhishek.pali...@aricent.com
From: David Daney david.da...@cavium.com
commit 35d0470668cca234e49ed35342b3f9a0eec8355c upstream
The fast handler only supports 64-bit kernels.
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Andreas Herrmann
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