Hi Everyone,
thank you for all your feedback. I did some more research, datasheet
reading and calculations to answer everything properly. While doing this
I oscillated back and forth between possible and not possible, now I'm
convinced that it will work :)
## Concept/Idea
The idea would be to use a FT601 with some glue/clock-logic supporting
only USB3 for data capturing.
Important is to use USB3 in bulk transfer and that the FT601 is the only
USB3 device on the bus.
The datasheet of the FT601 claims 100 MB continues data stream and 400
MB in burst with USB3 mode, so these settings would be an possible:
- 8ch @ 100 MHz: 1 Byte x 100 MHz = 95.36 MB/s or
- 16ch @ 50 MHz: 2 Byte x 50 MHz = 95.36 MB/s or
- 32ch @ 25 MHz: 4 Byte x 25 MHz = 95.36 MB/s
The FT601 has a 16kB (16384 bytes) FIFO.
Sampling 8 channel with 100 MHz would mean 1 byte per 10ns.
16384 bytes x 10 ns = 163.84µs
So the FIFO could hold data for 163.84µs.
## USB Timing
USB1 and USB2 are electrically based on one bidirectional differential
pair, meaning the Host or the Device can send data, not both together.
In practice the host polls the device every (micro)frame and that's the
fines time grid, the device can send data back to the host.
USB1 frame: 1ms
USB2 micro-frame: 125µs
It might already work with USB2 since the buffer can data for 164µs and
the USB2 timing grid is 125µs. But its highly unlikely that data can be
send on every micro-frame with USB bulk or interrupt transfer.
USB3 uses a differential lane, meaning one unidirectional differential
pair for Transmit and one for Receive. Host and device can send data
simultaneously. It also uses 125 µs micro frames for communications, but
uses a credit based system, meaning that the device is allowed to
transmit a certain amount of data without further permission.
1 credit = 1 packet (1024 byte)
Up to 256 credits per endpoint are possible; meaning 256kB without
further permission. Every transmission decreases the credit count, while
every micro frame the Host will update the credits. In practice 8-16
credits are typical.
USB3 Bulk transfer can occupy the entire micro frame bandwidth as long
as the host grants enough credits.
USB3 max data rate: 5Gb/s x 8/10 => 500 MB/s
USB3 max. data per micro frame: 600 MB/s * 125µs = 62.5 kB
FIFO data per micro frame:12.5 kB
16 USB3 credits would already work.
With this mechanism the device can send data to the host continuously,
resulting in a stream-like h.
Please let me know if you find any mistakes in my calculations.
## open questions
Can anyone answer or help with those questions:
1. How many credits does the FT601 get from the USB Host and can those
be change within the driver?
2. Could someone check the USB descriptors of the FT601 with "lsusb -v"
on a linux machine and share the output?
3. Is it possible to change the settings/mode of the FT601 with Lambda
Concept driver?
4. Which FT601 board are you guys using? Anyone using the evaluation
board UMFT60x?
Best,
Dan
On 10/16/25 23:41, Ivan Wick wrote:
Hi Dan,
I see on the Sigrok wiki that there has been some prior hardware
designed with the FT601: https://sigrok.org/wiki/CoLA
This uses the FT601 for a host interface, and logic signals are read
by an FPGA which can also do multiplexing etc.
But if I understood your idea correctly, it is to read logic signals
directly into the FT601 FIFOs without another chip, which is a
simpler, less expensive design.
Anyway, there is a barrier to using the FT601 chip: "The CoLA does not
have integration into Sigrok and Pulseview. This is because the used
FT601 driver is from FTDI and is closed source. This is the reason
that prevents the software from being released under Sigrok compatible
licence."
The closed source driver mentioned is D3xx:
https://ftdichip.com/drivers/d3xx-drivers/
So we could probably get an FT601 device working "out-of-tree" using
the proprietary driver, but I couldn't find a free software library
(analogous to libftdi) to drive the FT601.
On Wed, Oct 15, 2025 at 4:36 AM Daniel Tzschentke <[email protected]> wrote:
Hi Everyone,
Thanks a lot for Sigrok!
Recently I came across this USB3 (super speed) chip: FT601 from FTDI
https://ftdichip.com/products/ft601q-b/
It's a 32 bit sync FIFO to USB3 bridge and intended for parallel
camera
interfaces.
My first thought was, that it should be pretty straight forward to
build
a 32 channel 100 MHz logic analyzer with it.
I was thinking of an open source/community logic analyzer made for
Sigrok - schematic and pcb I know how to do, but I have no idea
how to
support the chip in Sigrok - would anyone be up for taking care of
the
Sigrok support?
I could send out some PCBs to developer from the first test batch but
would also upload all the kicad files (sch, pcb, bom, gbr, ...) to a
public github repo, so anyone could order PCBs.
What do you guys think?
Best,
Dan
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