3 Level Cache hierarchy

[zhadji01]

Hi,

I want to build a 3 level cache hierarchy with private l1s, l2 and a  
shared L3 cache (like the Xeon chip) for the CMP.L2SharedNuca.OoO and  
CMP.L2Shared.Trace simulators. Can I have any suggestions on how to do  
it?

thanks - Zacharias Hadjilambrou