The trace simulator is fairly simple. All you have to do is to change the L2 as FastCache and your newly added L3 as FastCMPCache. Then modify the wiring section and put the L3 between L2 and memory.
Regards, Mahmood ________________________________________ From: [email protected] [[email protected]] Sent: Sunday, November 18, 2012 8:48 PM To: [email protected] Subject: 3 Level Cache hierarchy Hi, I want to build a 3 level cache hierarchy with private l1s, l2 and a shared L3 cache (like the Xeon chip) for the CMP.L2SharedNuca.OoO and CMP.L2Shared.Trace simulators. Can I have any suggestions on how to do it? thanks - Zacharias Hadjilambrou
