Dear Abu, Sorry for the delay - we were evaluating the current state of >16 processor support in OoO simulators.
The current version of Flexus does not support 64 processors/cores in OoO timing. As you pointed out, the issue is that Simics leaves gaps in the numbering of processors. The DecoupledFeeder supports 64 processors (look at createTracers() in SimicsTracer.cpp), but portions of the out-of-order core that talk directly with Simics do not. We are working on a patch to enable support for 64 processors - we expect this to be ready in a couple weeks. Cheers, Stephen Somogyi On Thu, 8 Nov 2007, Abu Saad Papa wrote: > I had sent this post earliar. I am still trying to form a DSM with 64 > cores but not successful so far, any help will be highly appreciated. > > > > Hi, > > I am trying to use DSMFlex.OoO with 64 cores. As per the following thread > > > > https://sos.ece.cmu.edu/pipermail/simflex/2006-August/000247.html > > > > I made changes to FastBus component. After these changes there was no > > error when creating flexpoints using TraceFlex. > > Then when running the timing job, first the simulation was not moving > > forward after this point > > > > 1481 <ComponentManager.cpp:127> {0}- Loading state: 00-directory > > 1482 <DirectoryImpl.cpp:289> {0}- 00-directory couldn't find checkpoint > > 00-directory. Using flex_state_in/00-directory-tflex instead. > > > > I tried waiting for a long time still there was no progress. Later I made > > some changes in DirectoryImpl.cpp ( I changed all 'unsigned long' to > > 'unsigned long long'). This time there was progress in the simulation but > > I got stuck at this place > > > > 1734 <ComponentManager.cpp:127> {0}- Loading state: 61-nic > > 1735 <ComponentManager.cpp:127> {0}- Loading state: 62-nic > > 1736 <ComponentManager.cpp:127> {0}- Loading state: 63-nic > > 1737 <ComponentManager.cpp:127> {0}- Loading state: sys-network > > 1738 <ComponentManager.cpp:127> {0}- Loading state: sys-memory-map > > 1739 <MemoryMapImpl.cpp:322> {0}- Page map file page_map.out was not > > found. > > 1740 <ComponentManager.cpp:127> {0}- Loading state: sys-magic-break > > 1741 <ComponentManager.cpp:131> {0}- Done loading. > > 1742 <mai_api.cpp:151> {3}- CPU[8] Registering for interrupts > > 1743 <mai_api.cpp:151> {4}- CPU[2] Registering for interrupts > > ... > > ... > > ... > > 1805 <mai_api.cpp:151> {35}- CPU[40] Registering for interrupts > > 1806 <component.hpp:267> (<undefined>[<undefined>]) {55}- Assertion > > failed: ((!(anIndex < theWidth))) : Component: prot_eng Index: 81 Width: > > 64 > > (*** Simics ***) Simics getting shaky, switching to 'safe' mode. > > (*** Simics ***) Simics (main thread) received an abort signal, probably > > an assertion. > > pure virtual method called > > terminate called without an active exception > > (*** Simics ***) Simics getting shaky, switching to 'safe' mode. > > (*** Simics ***) Simics (main thread) received an abort signal, probably > > an assertion. > > > > I am getting back to the prompt after this error. I tried removing all > > the DBG_Assert( Index < Width) check by commenting them but still am > > getting the following error at the same stage namely, > > > > 1742 <mai_api.cpp:151> {3}- CPU[8] Registering for interrupts > > 1743 <mai_api.cpp:151> {4}- CPU[2] Registering for interrupts > > ... > > ... > > ... > > 1805 <mai_api.cpp:151> {35}- CPU[40] Registering for interrupts > > (*** Simics ***) Simics getting shaky, switching to 'safe' mode. > > (*** Simics ***) Simics (main thread) received an abort signal, probably > > an assertion. > > pure virtual method called > > terminate called without an active exception > > (*** Simics ***) Simics getting shaky, switching to 'safe' mode. > > (*** Simics ***) Simics (main thread) received an abort signal, probably > > an assertion. > > > > The index number of the 64 cores in the simics is varying from 0-23, > > 32-55 and 64-79. I think the problem lies here, the index numbers are > > not varying from 0-63!!! But I am not sure whether this is the cause > > for simics to get an error even after commenting the DBG_Assert( Index > > < Width) check. I hope someone has tried this earliar and have come > > with some solution to it. Please help me in getting a DSMFlex.OoO > > system with 64 cores. > > > > -- Abu Saad Papa > > > > > > _______________________________________________ > > SimFlex mailing list > > [email protected] > > https://sos.ece.cmu.edu/mailman/listinfo/simflex > > SimFlex web page: http://www.ece.cmu.edu/~simflex > > > > > -- > Abu Saad Papa > http://research.iiit.net/~abu_saad/ > M.S VLSI > IIIT, Hyderabad. > > "GOD GIVES MAN GETS ........ > GOD FORGIVES MAN FORGETS...." > > > _______________________________________________ > SimFlex mailing list > [email protected] > https://sos.ece.cmu.edu/mailman/listinfo/simflex > SimFlex web page: http://www.ece.cmu.edu/~simflex > From bramad2 at lsu.edu Mon Nov 12 13:37:26 2007 From: bramad2 at lsu.edu (Balachandran Ramadass) List-Post: [email protected] Date: Mon Nov 12 17:17:41 2007 Subject: [Simflex] where did dependency logic implemented. Message-ID: <[email protected]> hi Thanks for your previous mail. In re-order buffer we have set of instructions . In these instructions some instruction depends on the load instruction . here i am trying to find out which instruction in re-order buffere depend on load instruction. please tell me which file or function this logic is implemented in the simflex. Thanking you Bala > ----- Original Message ----- > From: "Thomas Wenisch" <[email protected]> > To: "SimFlex software support" <[email protected]> > Subject: Re: [Simflex] where did dependency logic implemented. > Date: Mon, 29 Oct 2007 18:03:31 -0400 (EDT) > > > > On Mon, 29 Oct 2007, Balachandran Ramadass wrote: > > > hi > > > > 1.)i am trying to identify the number of dependency insctruction > > for each load instruction in load store queue. please tell me in > > which file or which function dependency logic is implemented > > inside uArch directory for out of order simulation. > > The LSQ functionality you care about is in > components/uArch/CoreModel/memforward.cpp. In particular, loads > search for a matching preceding store in snoopStores(), while > stores finding matching succeeding loads in updateDependantLoads(). > > > > > 2) where did the branch predection logic implemented . I need to > > check the branch prediction feed back for the branch instruction. > > > > The branch predictor is in components/Common/BranchPredictor.cpp. > > Best Regards, > -Thomas Wenisch > > > > Thanking you > > Bala > > Louisiana state university > > > > > > _______________________________________________ > > SimFlex mailing list > > [email protected] > > https://sos.ece.cmu.edu/mailman/listinfo/simflex > > SimFlex web page: http://www.ece.cmu.edu/~simflex > > > _______________________________________________ > SimFlex mailing list > [email protected] > https://sos.ece.cmu.edu/mailman/listinfo/simflex > SimFlex web page: http://www.ece.cmu.edu/~simflex >
