Lars,
SimH knows nothing of the internal structure of simulators, so I'm
skeptical of a SimH-level solution. However, a simulator-specific
interface can be built.
As an example, I am finishing up the UC15, which is exactly what you
describe - a PDP11 that is connected to the memory of a PDP15 and
controlled via a cross-connected paralllel link. The PDP11 acts as an IO
processor for the PDP15.
I have not solved all the problems. The solution requires a multi-core
(or other kind of SMP) system, with one core per simulator. It probably
depends on in-order writes and strong cache consistency semantics. And
it definitely depends on tight polling, which causes the cores to run
flat out (unsuitable for mobile devices).
Bob
On 1/18/2018 5:29 AM, simh-requ...@trailing-edge.com wrote:
Message: 4
Date: Thu, 18 Jan 2018 10:12:13 +0000
From: Lars Brinkhoff<l...@nocrew.org>
To:simh@trailing-edge.com
Subject: [Simh] External bus interface
Message-ID:<7wtvvjearm....@junk.nocrew.org>
Content-Type: text/plain
Hello,
I wrote a GitHub issue about this, but maybe it's better to bring it up
for discussion on the mailing list. So I'll copy the text here:
Richard Cornwell's KA10 simulator is getting ready. At MIT, there were
PDP-11s connected to the PDP-10 memory and I/O busses. The 11s acted as
dedicated I/O processors. Some of us are interested in recreating
configurations similar to this. For example, MIT-AI had a PDP-11
connected to control a number of graphical terminals called Knight TVs.
And another PDP-11 for CHAOS networking.
To hook up separate simulator processes this way, I suppose there should
be some kind of bus interface for SIMH. The interface would have to
support memory transfers, interrupt signals, etc.
Would it be feasible to create such a bus interface?
Best regards,
Lars Brinkhoff
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