Yes, in separate processes. They use shared memory sections to
communicate - one as main memory, one as control state.
/Bob
On 1/18/2018 12:26 PM, Lars Brinkhoff wrote:
Hello,
Thanks, that's good to know. It's encouraging that something is
underway.
Are the machines running inside the same process? I was vaguely
thinking about running machines as separate processes, with some
communication mechanism between them. Maybe shared memory, maybe
something else. It wouldn't even have to be SimH in both ends.
But I'll take what I can get!
Best regards,
Lars Brinkhoff
SimH knows nothing of the internal structure of simulators, so I'm
skeptical of a SimH-level solution. However, a simulator-specific
interface can be built.
As an example, I am finishing up the UC15, which is exactly what you
describe - a PDP11 that is connected to the memory of a PDP15 and
controlled via a cross-connected paralllel link. The PDP11 acts as an
IO processor for the PDP15.
I have not solved all the problems. The solution requires a multi-core
(or other kind of SMP) system, with one core per simulator. It
probably depends on in-order writes and strong cache consistency
semantics. And it definitely depends on tight polling, which causes
the cores to run flat out (unsuitable for mobile devices).
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