KY1K wrote:
> Below is a copy of a message I posted to the softrock-40 group. Some
> who monitor here might be interested as well.
>
> Message follows:
>
>
> -------------------------------------------------------------
>
> Greetings all,
>
> I simulated (Spice) the sluggish turn off times of the FST3125 cmos
> switch. Due to the slower turn off time, there is overlap in the
> conduction of adjacent switches...meaning that 2 switches are
> momentarily conducting at the same time. I found the conversion gain
> drops very quickly once the 25 percent duty cycle is exceeded and
> that this condition should be avoided for good results.
>
> I had hoped to release the data in a more polished form, but here is
> the summary of the losses for each HF band.
>
> These are relative conversion gains and were obtained by applying 4
> nS overalp on each analog switch. Note that ~4 ns overlap is the
> actual overlap that exists in the FST3125 and similar technology cmos
> analog switches we use in softrock's/QSD's today.
>
> On 50* Mhz, the conversion gain is down 20.3 db (relative to a
> perfect 25-25-25-25 duty cycle).
>
> On 28* Mhz, the conversion gain is down 14.2 db (relative to a
> perfect 25-25-25-25 duty cycle).
>
> On 14* Mhz, the conversion gain is down 8.7 db (relative to a perfect
> 25-25-25-25 duty cycle).
>
> On 7* Mhz, the conversion gain is down 7.6 db (relative to a perfect
> 25-25-25-25 duty cycle).
>
> On 3.5* Mhz, the conversion gain is down 4.6 db (relative to a
> perfect 25-25-25-25 duty cycle).
>
> *4 ohm R(on), a 10 Megohm R(off), with 4 nS overlap, .01 uF
> integrating caps.
>
> I also have the Spice model(s) used, and a graph showing relative
> conversion gain vs the switch duty cycle for ranges between 5 and 45
> percent. The graph is a crude gif file, but is legible. Email me OFF
> LIST if you would like any of the data.
>
> Regards,
>
> Art
>
>
>
>
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Art,
I am curious about your conversion loss data. Did you try to replicate
the QSD of the SR4? Did you include the source impedance?
I have done a similar simulation using an old version of Electronic
WorkBench (EWB). However, I simulated 7 MHz only, but with switch on
times from 5% to 55% of a period. Also, I used 0.1 uF caps. I am
assuming that operation at higher frequencies will be similar to 7 MHz,
but with an increased % on-time, for a given turn-off delay. I also get
a drop in conversion gain for on-times greater than 25%. Using the
"Virtual Oscilloscope" in EWB, it is apparent that the source is loaded
more heavily when two switches are simultaneously closed. During two of
the overlaps, two load resistors are connected (to their respective
caps), reducing the signal from the source. During the other two
overlaps, two caps are connected to the same resistor. This also
reduces the signal due to charge sharing between the caps. My model
predicts only about 1 dB loss at 7 MHz due to the overlaps. With 25% of
a cycle /overlap/, the loss increases to between 5 and 6 dB. Obviously
my model must be using a different circuit.
Can you post a schematic of your simulated circuit, or at least let me
know which of the SRs you have simulated. With this information, I can
modify my model and verify your results.
Thanks for the report.
73, Milt
W8NUE
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