Jitter Paper from Cardinal Components, Inc. http://WWW.CARDINALXTAL.COM/
Jitter: Frequency instability in a crystal-controlled clock is the unintentional modulation of the generated signal. The unintentional modulation is due to noise generated by the active device in the oscillator stage and buffer stages, crystal noise, and noise conducted into the oscillator by the power source. The crystal clock can oscillate at any frequency within the loaded bandwidth of the oscillator resonator. Although the crystal resonator bandwidth is extremely narrow, the signal generated by the oscillator does have some instability. DESIGN CONSIDERATIONS: The system designer must consider several factors when using clock oscillator in circuits that are sensitive to clock jitter. There are two types of jitter present in the clock signal. One is random jitter and the other is jitter caused by non-random events. The internal random noise and internal modulation cause by spurious internal frequencies generated is the responsibility of the oscillator manufacturer. The random noise and spurious frequencies present on the ground system and power supply bus must be minimized by the system or board level manufacturer. Several essential design features can greatly reduce the chance of introducing noise that will unintentionally modulate the clock oscillator. Be sure that there is an adequate single ground plane to prevent ground bounce and spurious oscillations. Since a 100 MHz clock with a 1 nanosecond rise and fall time generates odd harmonics frequencies well into the microwave region, excellent RF and Microwave power line bypassing is very important. A minimum of 4.7 uF in parallel with a 0.01 uF is the recommended by-pass on the oscillator input power leads. The signal lines from the oscillator to the load must be short and have low inductance. If inductance is present on the signal line, this will cause ringing on the output waveform due to the stray capacitance to ground. The power supply bus should be free of system spurious signals, voltage regulator noise, and ripple. Be sure the clock is loaded properly and is not reflecting spurious signals back into the clock output. The output waveform must have clean rise and fall edges. Summary by ka9rza: For home brewing of signal sources, the control of jitter via removal of all sources of oscillator modulation from the VFO or VCO (if you are building pll or H&P circuits) can be achieved if you remember that you are filtering out all modulation avenues that are possible. Hence use allot of decoupling capacitors as needed. Also, to insure that bad swr on the VFO does not result in undesired effects; consider the loading of the VFO and use a buffer amplifier to reduce loading. Modulation loading effects that can reach the buffer is reduced by it being in the way of the VFO. posted by Dan ka9rza _____________________________________________________________________ PrivatePhone - FREE telephone number & voicemail. A number so private, you can make it public. http://www.privatephone.com ------------------------ Yahoo! Groups Sponsor --------------------~--> See what's inside the new Yahoo! Groups email. http://us.click.yahoo.com/2pRQfA/bOaOAA/yQLSAA/ELTolB/TM --------------------------------------------------------------------~-> Yahoo! Groups Links <*> To visit your group on the web, go to: http://groups.yahoo.com/group/soft_radio/ <*> To unsubscribe from this group, send an email to: [EMAIL PROTECTED] <*> Your use of Yahoo! Groups is subject to: http://docs.yahoo.com/info/terms/
