Module Name: src
Committed By: snj
Date: Sat Feb 27 20:32:04 UTC 2010
Modified Files:
src/sys/arch/mips/mips [matt-nb5-mips64]: mipsX_subr.S
Log Message:
Fix some typos in comments.
To generate a diff of this commit:
cvs rdiff -u -r1.26.36.1.2.27 -r1.26.36.1.2.28 \
src/sys/arch/mips/mips/mipsX_subr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/mipsX_subr.S
diff -u src/sys/arch/mips/mips/mipsX_subr.S:1.26.36.1.2.27 src/sys/arch/mips/mips/mipsX_subr.S:1.26.36.1.2.28
--- src/sys/arch/mips/mips/mipsX_subr.S:1.26.36.1.2.27 Sat Feb 27 07:58:52 2010
+++ src/sys/arch/mips/mips/mipsX_subr.S Sat Feb 27 20:32:04 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: mipsX_subr.S,v 1.26.36.1.2.27 2010/02/27 07:58:52 matt Exp $ */
+/* $NetBSD: mipsX_subr.S,v 1.26.36.1.2.28 2010/02/27 20:32:04 snj Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -671,7 +671,7 @@
/*
* We need to find out if this was due to a T_BREAK and if so
- * turn off interrupts in addition to clearing the execption level.
+ * turn off interrupts in addition to clearing the exception level.
*/
li v1, 1 << T_BREAK # make a mask of T_BREAK
sll t0, a1, MIPS_CR_EXC_CODE_SHIFT # shift exc code to low 5 bits
@@ -1205,7 +1205,7 @@
* Clear interrupt enable
*/
mfc0 v0, MIPS_COP_0_STATUS # read it
- xor v0, MIPS_SR_INT_IE # disable interrutps
+ xor v0, MIPS_SR_INT_IE # disable interrupts
mtc0 v0, MIPS_COP_0_STATUS # write it
COP0_SYNC
nop
@@ -1957,7 +1957,7 @@
* mipsN_VCED --
*
* Handle virtual coherency exceptions.
- * Called directly from the mips3 execption-table code.
+ * Called directly from the mips3 exception-table code.
* only k0, k1 are available on entry
*
* Results:
@@ -1965,7 +1965,7 @@
*
* Side effects:
* Remaps the conflicting address as uncached and returns
- * from the execption.
+ * from the exception.
*
* NB: cannot be profiled, all registers are user registers on entry.
*
@@ -2631,7 +2631,7 @@
tlbwi # now write the invalid TLB
COP0_SYNC
- mtc0 a3, MIPS_COP_0_TLB_HI # retore the addr for new TLB
+ mtc0 a3, MIPS_COP_0_TLB_HI # restore the addr for new TLB
COP0_SYNC
nop
nop
