Module Name: src
Committed By: bouyer
Date: Wed Mar 10 19:23:57 UTC 2010
Modified Files:
src/sys/dev/ic: ahcisata_core.c
Log Message:
ahcisata_core.c 1.23 cause long drive probe (31s, reported by
Roy Marples), or other devices misbehavior probably due to interrupts issues
(reported by Jukka Ruohonen). Back it out and do the following changes:
- clear port interrupt register before ahci_channel_start() which enables
interrupts
- wait 500ms after sata_reset_interface() before touching SERROR register.
This is what seems to fix the issue I'm seeming on ESB2 controller.
- The 31s delay didn't cause the probe to fail because of a mismatch
in loop index comparison; use a #define for delay after reset
instead of numeric values, to avoid this kind of bugs in the
future.
To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24 src/sys/dev/ic/ahcisata_core.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/ic/ahcisata_core.c
diff -u src/sys/dev/ic/ahcisata_core.c:1.23 src/sys/dev/ic/ahcisata_core.c:1.24
--- src/sys/dev/ic/ahcisata_core.c:1.23 Tue Feb 23 21:38:36 2010
+++ src/sys/dev/ic/ahcisata_core.c Wed Mar 10 19:23:57 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: ahcisata_core.c,v 1.23 2010/02/23 21:38:36 bouyer Exp $ */
+/* $NetBSD: ahcisata_core.c,v 1.24 2010/03/10 19:23:57 bouyer Exp $ */
/*
* Copyright (c) 2006 Manuel Bouyer.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.23 2010/02/23 21:38:36 bouyer Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.24 2010/03/10 19:23:57 bouyer Exp $");
#include <sys/types.h>
#include <sys/malloc.h>
@@ -99,6 +99,8 @@
#endif /* NATAPIBUS */
#define ATA_DELAY 10000 /* 10s for a drive I/O */
+#define ATA_RESET_DELAY 31000 /* 31s for a drive reset */
+#define AHCI_RST_WAIT (ATA_RESET_DELAY / 10)
const struct ata_bustype ahci_ata_bustype = {
SCSIPI_BUSTYPE_ATA,
@@ -507,23 +509,26 @@
chp->ch_queue->active_xfer->c_kill_xfer(chp,
chp->ch_queue->active_xfer, KILL_RESET);
}
+ tsleep(&sc, PRIBIO, "ahcirst", mstohz(500));
+ /* clear port interrupt register */
+ AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
+ /* clear SErrors and start operations */
+ ahci_channel_start(sc, chp);
/* wait 31s for BSY to clear */
- for (i = 0; i <3100; i++) {
+ for (i = 0; i <AHCI_RST_WAIT; i++) {
tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel));
if ((((tfd & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT)
& WDCS_BSY) == 0)
break;
tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10));
}
- if (i == 1500)
+ if (i == AHCI_RST_WAIT)
aprint_error("%s: BSY never cleared, TD 0x%x\n",
AHCINAME(sc), tfd);
AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10),
DEBUG_PROBE);
/* clear port interrupt register */
AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
- /* and start channel */
- ahci_channel_start(sc, chp);
return;
}
@@ -568,15 +573,20 @@
switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol,
achp->ahcic_sstatus)) {
case SStatus_DET_DEV:
+ tsleep(&sc, PRIBIO, "ahcidv", mstohz(500));
+ /* clear port interrupt register */
+ AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
+ /* clear SErrors and start operations */
+ ahci_channel_start(sc, chp);
/* wait 31s for BSY to clear */
- for (i = 0; i <3100; i++) {
+ for (i = 0; i <AHCI_RST_WAIT; i++) {
sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel));
if ((((sig & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT)
& WDCS_BSY) == 0)
break;
tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10));
}
- if (i == 1500) {
+ if (i == AHCI_RST_WAIT) {
aprint_error("%s: BSY never cleared, TD 0x%x\n",
AHCINAME(sc), sig);
return;
@@ -599,8 +609,6 @@
splx(s);
/* clear port interrupt register */
AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
- /* start channel */
- ahci_channel_start(sc, chp);
/* and enable interrupts */
AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel),
AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS |
