On Wed, Mar 31, 2010 at 04:06:47PM -0500, David Young wrote: > > > > bus_space_barrier() doesn't flush ... barriers only enforce > > the ordering of operations (and, of course, with respect to > > non-overlapping addresses ... obviously reads after writes of the > > same address in code will be enforced on the bus without an explicit > > barrier). > > Right. Putting the question another way, Is it important that reading > the register we wrote "lands" the write as a side-effect?
It will have that effect, and, in many cases (think of writes being 'posted' on the hardware itself - inside the final PCI device) a readback is the only way to actually force a write to complete. This is true almost regardless of the cpu and bus architecture. > Do we expect that on sparc64, the bus barrier also "lands" the > write as a side-effect? The bus barrier is extremely unlikely to be able to get the write past the first PCI bus. The usual time this causes grief is when the write is a request to remove an IRQ, and is executed immediately before the ISR returns. David -- David Laight: da...@l8s.co.uk