Module Name: src Committed By: jmcneill Date: Wed Jun 12 10:03:28 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Route all interrupts to the primary PE by default
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
