Module Name: src Committed By: jmcneill Date: Sun Jun 16 11:05:59 UTC 2019
Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: - Disable MSI/MSI-X when making changes - MSI: Write the vector count to the Multi Message Enable (MME) field - MSI: Set DATA to the first LPI number, not the last To generate a diff of this commit: cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/arm/cortex/gicv3_its.c diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.12 src/sys/arch/arm/cortex/gicv3_its.c:1.13 --- src/sys/arch/arm/cortex/gicv3_its.c:1.12 Wed Jun 12 21:02:07 2019 +++ src/sys/arch/arm/cortex/gicv3_its.c Sun Jun 16 11:05:58 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3_its.c,v 1.12 2019/06/12 21:02:07 jmcneill Exp $ */ +/* $NetBSD: gicv3_its.c,v 1.13 2019/06/16 11:05:58 jmcneill Exp $ */ /*- * Copyright (c) 2018 The NetBSD Foundation, Inc. @@ -32,7 +32,7 @@ #define _INTR_PRIVATE #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.12 2019/06/12 21:02:07 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.13 2019/06/16 11:05:58 jmcneill Exp $"); #include <sys/param.h> #include <sys/kmem.h> @@ -336,7 +336,7 @@ gicv3_its_device_map(struct gicv3_its *i } static void -gicv3_its_msi_enable(struct gicv3_its *its, int lpi) +gicv3_its_msi_enable(struct gicv3_its *its, int lpi, int count) { const struct pci_attach_args *pa = its->its_pa[lpi - its->its_pic->pic_irqbase]; pci_chipset_tag_t pc = pa->pa_pc; @@ -347,6 +347,15 @@ gicv3_its_msi_enable(struct gicv3_its *i if (!pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL)) panic("gicv3_its_msi_enable: device is not MSI-capable"); + ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); + ctl &= ~PCI_MSI_CTL_MSI_ENABLE; + pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl); + + ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); + ctl &= ~PCI_MSI_CTL_MME_MASK; + ctl |= __SHIFTIN(ilog2(count), PCI_MSI_CTL_MME_MASK); + pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl); + const uint64_t addr = its->its_base + GITS_TRANSLATER; ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); if (ctl & PCI_MSI_CTL_64BIT_ADDR) { @@ -394,6 +403,10 @@ gicv3_its_msix_enable(struct gicv3_its * if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL)) panic("gicv3_its_msix_enable: device is not MSI-X-capable"); + ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); + ctl &= ~PCI_MSIX_CTL_ENABLE; + pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl); + const uint64_t addr = its->its_base + GITS_TRANSLATER; const uint64_t entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec; bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, (uint32_t)addr); @@ -453,7 +466,8 @@ gicv3_its_msi_alloc(struct arm_pci_msi * __SHIFTIN(n, ARM_PCI_INTR_MSI_VEC) | __SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME); - gicv3_its_msi_enable(its, lpi); + if (n == 0) + gicv3_its_msi_enable(its, lpi, *count); /* * Record target PE