Module Name: src
Committed By: jmcneill
Date: Mon Jun 17 00:49:55 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gic_v2m.c
Log Message:
- Disable MSI/MSI-X when making changes
- MSI: Write the vector count to the Multi Message Enable (MME) field
- MSI: Set DATA to the first LPI number, not the last
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/cortex/gic_v2m.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic_v2m.c
diff -u src/sys/arch/arm/cortex/gic_v2m.c:1.5 src/sys/arch/arm/cortex/gic_v2m.c:1.6
--- src/sys/arch/arm/cortex/gic_v2m.c:1.5 Fri Dec 7 17:56:41 2018
+++ src/sys/arch/arm/cortex/gic_v2m.c Mon Jun 17 00:49:55 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gic_v2m.c,v 1.5 2018/12/07 17:56:41 jakllsch Exp $ */
+/* $NetBSD: gic_v2m.c,v 1.6 2019/06/17 00:49:55 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,10 +32,11 @@
#define _INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.5 2018/12/07 17:56:41 jakllsch Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.6 2019/06/17 00:49:55 jmcneill Exp $");
#include <sys/param.h>
#include <sys/kmem.h>
+#include <sys/bitops.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
@@ -90,7 +91,7 @@ gic_v2m_msi_available_spi(struct gic_v2m
}
static void
-gic_v2m_msi_enable(struct gic_v2m_frame *frame, int spi)
+gic_v2m_msi_enable(struct gic_v2m_frame *frame, int spi, int count)
{
const struct pci_attach_args *pa = frame->frame_pa[spi];
pci_chipset_tag_t pc = pa->pa_pc;
@@ -101,6 +102,15 @@ gic_v2m_msi_enable(struct gic_v2m_frame
if (!pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL))
panic("gic_v2m_msi_enable: device is not MSI-capable");
+ ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
+ ctl &= ~PCI_MSI_CTL_MSI_ENABLE;
+ pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
+
+ ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
+ ctl &= ~PCI_MSI_CTL_MME_MASK;
+ ctl |= __SHIFTIN(ilog2(count), PCI_MSI_CTL_MME_MASK);
+ pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
+
const uint64_t addr = frame->frame_reg + GIC_MSI_SETSPI;
ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
if (ctl & PCI_MSI_CTL_64BIT_ADDR) {
@@ -148,6 +158,10 @@ gic_v2m_msix_enable(struct gic_v2m_frame
if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL))
panic("gic_v2m_msix_enable: device is not MSI-X-capable");
+ ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
+ ctl &= ~PCI_MSIX_CTL_ENABLE;
+ pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
+
const uint64_t addr = frame->frame_reg + GIC_MSI_SETSPI;
const uint64_t entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec;
bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, (uint32_t)addr);
@@ -210,10 +224,10 @@ gic_v2m_msi_alloc(struct arm_pci_msi *ms
__SHIFTIN(spi, ARM_PCI_INTR_IRQ) |
__SHIFTIN(n, ARM_PCI_INTR_MSI_VEC) |
__SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME);
-
- gic_v2m_msi_enable(frame, spi);
}
+ gic_v2m_msi_enable(frame, spi_base, *count);
+
return vectors;
}
