Module Name: src
Committed By: skrll
Date: Sat Aug 10 17:03:59 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: a9tmr_var.h a9wdt.c files.cortex
src/sys/arch/arm/fdt: files.fdt
Added Files:
src/sys/arch/arm/cortex: a9ptmr.c a9ptmr_var.h
src/sys/arch/arm/fdt: a9ptmr_fdt.c a9wdt_fdt.c
Log Message:
Add a driver for the A5/A9 Private timer.
While here FDTise the Watchdog driver.
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/cortex/a9ptmr.c \
src/sys/arch/arm/cortex/a9ptmr_var.h
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/cortex/a9tmr_var.h
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/cortex/a9wdt.c
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/cortex/files.cortex
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/fdt/a9ptmr_fdt.c \
src/sys/arch/arm/fdt/a9wdt_fdt.c
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/arm/fdt/files.fdt
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/a9tmr_var.h
diff -u src/sys/arch/arm/cortex/a9tmr_var.h:1.6 src/sys/arch/arm/cortex/a9tmr_var.h:1.7
--- src/sys/arch/arm/cortex/a9tmr_var.h:1.6 Wed Jun 20 05:01:39 2018
+++ src/sys/arch/arm/cortex/a9tmr_var.h Sat Aug 10 17:03:59 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: a9tmr_var.h,v 1.6 2018/06/20 05:01:39 hkenken Exp $ */
+/* $NetBSD: a9tmr_var.h,v 1.7 2019/08/10 17:03:59 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -54,6 +54,9 @@ void a9tmr_cpu_initclocks(void);
int a9tmr_intr(void *);
void a9tmr_update_freq(uint32_t);
void a9tmr_delay(unsigned int n);
+
+int a9ptmr_intr(void *);
+void a9ptmr_delay(unsigned int n);
#endif
#endif /* _ARM_CORTEX_A9TMR_VAR_ */
Index: src/sys/arch/arm/cortex/a9wdt.c
diff -u src/sys/arch/arm/cortex/a9wdt.c:1.9 src/sys/arch/arm/cortex/a9wdt.c:1.10
--- src/sys/arch/arm/cortex/a9wdt.c:1.9 Sat Aug 10 16:50:23 2019
+++ src/sys/arch/arm/cortex/a9wdt.c Sat Aug 10 17:03:59 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: a9wdt.c,v 1.9 2019/08/10 16:50:23 skrll Exp $ */
+/* $NetBSD: a9wdt.c,v 1.10 2019/08/10 17:03:59 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: a9wdt.c,v 1.9 2019/08/10 16:50:23 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: a9wdt.c,v 1.10 2019/08/10 17:03:59 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -67,7 +67,7 @@ struct a9wdt_softc {
#define A9WDT_PERIOD_DEFAULT 12
#endif
-CFATTACH_DECL_NEW(a9wdt, sizeof(struct a9wdt_softc),
+CFATTACH_DECL_NEW(arma9wdt, sizeof(struct a9wdt_softc),
a9wdt_match, a9wdt_attach, NULL, NULL);
static bool attached;
@@ -192,7 +192,7 @@ a9wdt_attach(device_t parent, device_t s
sc->sc_memt = mpcaa->mpcaa_memt;
bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh,
- TMR_WDOG_BASE, TMR_WDOG_SIZE, &sc->sc_wdog_memh);
+ mpcaa->mpcaa_off1, TMR_WDOG_SIZE, &sc->sc_wdog_memh);
/*
* This runs at the ARM PERIPHCLOCK which should be 1/2 of the
Index: src/sys/arch/arm/cortex/files.cortex
diff -u src/sys/arch/arm/cortex/files.cortex:1.11 src/sys/arch/arm/cortex/files.cortex:1.12
--- src/sys/arch/arm/cortex/files.cortex:1.11 Mon Nov 12 12:56:05 2018
+++ src/sys/arch/arm/cortex/files.cortex Sat Aug 10 17:03:59 2019
@@ -1,4 +1,4 @@
-# $NetBSD: files.cortex,v 1.11 2018/11/12 12:56:05 jmcneill Exp $
+# $NetBSD: files.cortex,v 1.12 2019/08/10 17:03:59 skrll Exp $
defflag opt_cpu_in_cksum.h NEON_IN_CKSUM
@@ -37,7 +37,12 @@ device arma9tmr
attach arma9tmr at mpcorebus
file arch/arm/cortex/a9tmr.c arma9tmr
+# A9 MPcore Private Timer
+device arma9ptmr
+attach arma9ptmr at mpcorebus
+file arch/arm/cortex/a9ptmr.c arma9ptmr
+
# A9 MPcore Watchdog Timer
-device a9wdt: sysmon_wdog
-attach a9wdt at mpcorebus
-file arch/arm/cortex/a9wdt.c a9wdt
+device arma9wdt: sysmon_wdog
+attach arma9wdt at mpcorebus
+file arch/arm/cortex/a9wdt.c arma9wdt
Index: src/sys/arch/arm/fdt/files.fdt
diff -u src/sys/arch/arm/fdt/files.fdt:1.28 src/sys/arch/arm/fdt/files.fdt:1.29
--- src/sys/arch/arm/fdt/files.fdt:1.28 Wed Dec 5 21:43:33 2018
+++ src/sys/arch/arm/fdt/files.fdt Sat Aug 10 17:03:59 2019
@@ -1,4 +1,4 @@
-# $NetBSD: files.fdt,v 1.28 2018/12/05 21:43:33 jmcneill Exp $
+# $NetBSD: files.fdt,v 1.29 2019/08/10 17:03:59 skrll Exp $
include "dev/pckbport/files.pckbport"
@@ -17,6 +17,14 @@ device a9tmr: mpcorebus
attach a9tmr at fdt with a9tmr_fdt
file arch/arm/fdt/a9tmr_fdt.c a9tmr_fdt
+device a9ptmr: mpcorebus
+attach a9ptmr at fdt with a9ptmr_fdt
+file arch/arm/fdt/a9ptmr_fdt.c a9ptmr_fdt
+
+device a9wdt: mpcorebus
+attach a9wdt at fdt with a9wdt_fdt
+file arch/arm/fdt/a9wdt_fdt.c a9wdt_fdt
+
device gtmr: mpcorebus
attach gtmr at fdt with gtmr_fdt
file arch/arm/fdt/gtmr_fdt.c gtmr_fdt
Added files:
Index: src/sys/arch/arm/cortex/a9ptmr.c
diff -u /dev/null src/sys/arch/arm/cortex/a9ptmr.c:1.1
--- /dev/null Sat Aug 10 17:03:59 2019
+++ src/sys/arch/arm/cortex/a9ptmr.c Sat Aug 10 17:03:59 2019
@@ -0,0 +1,264 @@
+/* $NetBSD: a9ptmr.c,v 1.1 2019/08/10 17:03:59 skrll Exp $ */
+
+/*-
+ * Copyright (c) 2019 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Nick Hudson
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: a9ptmr.c,v 1.1 2019/08/10 17:03:59 skrll Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/device.h>
+#include <sys/kernel.h>
+
+#include <prop/proplib.h>
+
+#include <arm/cortex/a9tmr_reg.h>
+#include <arm/cortex/a9ptmr_var.h>
+
+#include <arm/cortex/mpcore_var.h>
+
+static struct a9ptmr_softc *a9ptmr_sc;
+
+static int a9ptmr_match(device_t, cfdata_t, void *);
+static void a9ptmr_attach(device_t, device_t, void *);
+
+struct a9ptmr_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_memt;
+ bus_space_handle_t sc_memh;
+
+ uint32_t sc_ctl;
+ uint32_t sc_freq;
+ uint32_t sc_load;
+
+ uint32_t sc_prescaler;
+};
+
+
+CFATTACH_DECL_NEW(arma9ptmr, sizeof(struct a9ptmr_softc),
+ a9ptmr_match, a9ptmr_attach, NULL, NULL);
+
+static bool attached;
+
+static inline uint32_t
+a9ptmr_read(struct a9ptmr_softc *sc, bus_size_t o)
+{
+ return bus_space_read_4(sc->sc_memt, sc->sc_memh, o);
+}
+
+static inline void
+a9ptmr_write(struct a9ptmr_softc *sc, bus_size_t o, uint32_t v)
+{
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, o, v);
+}
+
+/* ARGSUSED */
+static int
+a9ptmr_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct mpcore_attach_args * const mpcaa = aux;
+
+ if (attached)
+ return 0;
+
+ if (!CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid) &&
+ !CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid))
+ return 0;
+
+ if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0)
+ return 0;
+
+#if 0
+ /*
+ * This isn't present on UP A9s (since CBAR isn't present).
+ */
+ uint32_t mpidr = armreg_mpidr_read();
+ if (mpidr == 0 || (mpidr & MPIDR_U))
+ return 0;
+#endif
+
+ return 1;
+}
+
+
+static void
+a9ptmr_attach(device_t parent, device_t self, void *aux)
+{
+ struct a9ptmr_softc * const sc = device_private(self);
+ struct mpcore_attach_args * const mpcaa = aux;
+ prop_dictionary_t dict = device_properties(self);
+ char freqbuf[sizeof("XXX SHz")];
+ const char *cpu_type;
+
+
+ sc->sc_dev = self;
+ sc->sc_memt = mpcaa->mpcaa_memt;
+
+ bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh,
+ mpcaa->mpcaa_off1, TMR_PRIVATE_SIZE, &sc->sc_memh);
+
+ /*
+ * This runs at the ARM PERIPHCLOCK.
+ * The MD code should have setup our frequency for us.
+ */
+ if (!prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq)) {
+ dict = device_properties(parent);
+ prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq);
+ }
+
+ humanize_number(freqbuf, sizeof(freqbuf), sc->sc_freq, "Hz", 1000);
+
+ a9ptmr_sc = sc;
+ sc->sc_dev = self;
+ sc->sc_memt = mpcaa->mpcaa_memt;
+ sc->sc_memh = mpcaa->mpcaa_memh;
+
+ sc->sc_ctl = a9ptmr_read(sc, TMR_CTL);
+
+ sc->sc_prescaler = 1;
+ /*
+ * Let's hope the timer frequency isn't prime.
+ */
+ for (size_t div = 256; div >= 2; div--) {
+ if (sc->sc_freq % div == 0) {
+ sc->sc_prescaler = div;
+ break;
+ }
+ }
+ sc->sc_freq /= sc->sc_prescaler;
+
+ aprint_debug_dev(sc->sc_dev, ": freq %d prescaler %d", sc->sc_freq,
+ sc->sc_prescaler);
+ sc->sc_ctl = TMR_CTL_INT_ENABLE | TMR_CTL_AUTO_RELOAD | TMR_CTL_ENABLE;
+ sc->sc_ctl |= __SHIFTIN(sc->sc_prescaler - 1, TMR_CTL_PRESCALER);
+
+ sc->sc_load = (sc->sc_freq / hz) - 1;
+
+ a9ptmr_init_cpu_clock(curcpu());
+
+ aprint_naive("\n");
+ if (CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid)) {
+ cpu_type = "A5";
+ } else {
+ cpu_type = "A9";
+ }
+ aprint_normal(": %s Private Timer (%s)\n", cpu_type, freqbuf);
+
+ attached = true;
+}
+
+
+
+void
+a9ptmr_delay(unsigned int n)
+{
+ struct a9ptmr_softc * const sc = a9ptmr_sc;
+
+ KASSERT(sc != NULL);
+
+ uint32_t freq = sc->sc_freq ? sc->sc_freq :
+ curcpu()->ci_data.cpu_cc_freq / 2;
+ KASSERT(freq != 0);
+
+
+ const uint64_t counts_per_usec = freq / 1000000;
+ uint32_t delta, usecs, last, curr;
+
+ KASSERT(sc != NULL);
+
+ last = a9ptmr_read(sc, TMR_CTR);
+
+ delta = usecs = 0;
+ while (n > usecs) {
+ curr = a9ptmr_read(sc, TMR_CTR);
+
+ /* Check to see if the timer has wrapped around. */
+ if (curr < last)
+ delta += curr + (sc->sc_load - last);
+ else
+ delta += curr - last;
+
+ last = curr;
+
+ if (delta >= counts_per_usec) {
+ usecs += delta / counts_per_usec;
+ delta %= counts_per_usec;
+ }
+ }
+}
+
+
+void
+a9ptmr_cpu_initclocks(void)
+{
+ struct a9ptmr_softc * const sc __diagused = a9ptmr_sc;
+
+ KASSERT(sc->sc_dev != NULL);
+ KASSERT(sc->sc_freq != 0);
+
+}
+
+void
+a9ptmr_init_cpu_clock(struct cpu_info *ci)
+{
+ struct a9ptmr_softc * const sc = a9ptmr_sc;
+
+ /* Disable Private timer and acknowledge any event */
+ a9ptmr_write(sc, TMR_CTL, 0);
+ a9ptmr_write(sc, TMR_INT, TMR_INT_EVENT);
+
+ /*
+ * Provide the auto load value for the decrementing counter and
+ * start it.
+ */
+ a9ptmr_write(sc, TMR_LOAD, sc->sc_load);
+ a9ptmr_write(sc, TMR_CTL, sc->sc_ctl);
+
+}
+
+
+
+/*
+ * a9ptmr_intr:
+ *
+ * Handle the hardclock interrupt.
+ */
+int
+a9ptmr_intr(void *arg)
+{
+ struct clockframe * const cf = arg;
+ struct a9ptmr_softc * const sc = a9ptmr_sc;
+
+ a9ptmr_write(sc, TMR_INT, TMR_INT_EVENT);
+ hardclock(cf);
+
+ return 1;
+}
Index: src/sys/arch/arm/cortex/a9ptmr_var.h
diff -u /dev/null src/sys/arch/arm/cortex/a9ptmr_var.h:1.1
--- /dev/null Sat Aug 10 17:03:59 2019
+++ src/sys/arch/arm/cortex/a9ptmr_var.h Sat Aug 10 17:03:59 2019
@@ -0,0 +1,45 @@
+/* $NetBSD: a9ptmr_var.h,v 1.1 2019/08/10 17:03:59 skrll Exp $ */
+/*-
+ * Copyright (c) 2012 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_CORTEX_A9PTMR_VAR_
+#define _ARM_CORTEX_A9PTMR_VAR_
+
+#ifdef _KERNEL
+
+void a9ptmr_cpu_initclocks(void);
+
+struct cpu_info;
+void a9ptmr_init_cpu_clock(struct cpu_info *);
+
+int a9ptmr_intr(void *);
+void a9ptmr_delay(unsigned int n);
+#endif
+
+#endif /* _ARM_CORTEX_A9PTMR_VAR_ */
Index: src/sys/arch/arm/fdt/a9ptmr_fdt.c
diff -u /dev/null src/sys/arch/arm/fdt/a9ptmr_fdt.c:1.1
--- /dev/null Sat Aug 10 17:03:59 2019
+++ src/sys/arch/arm/fdt/a9ptmr_fdt.c Sat Aug 10 17:03:59 2019
@@ -0,0 +1,141 @@
+/* $NetBSD: a9ptmr_fdt.c,v 1.1 2019/08/10 17:03:59 skrll Exp $ */
+
+/*-
+ * Copyright (c) 2019 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Nick Hudson
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: a9ptmr_fdt.c,v 1.1 2019/08/10 17:03:59 skrll Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+
+#include <sys/device.h>
+#include <sys/intr.h>
+
+#include <arm/cortex/mpcore_var.h>
+#include <arm/cortex/a9ptmr_var.h>
+
+#include <dev/fdt/fdtvar.h>
+#include <arm/fdt/arm_fdtvar.h>
+
+static int a9ptmr_fdt_match(device_t, cfdata_t, void *);
+static void a9ptmr_fdt_attach(device_t, device_t, void *);
+
+static void a9ptmr_fdt_cpu_hatch(void *, struct cpu_info *);
+
+struct a9ptmr_fdt_softc {
+ device_t sc_dev;
+ struct clk *sc_clk;
+};
+
+CFATTACH_DECL_NEW(a9ptmr_fdt, sizeof(struct a9ptmr_fdt_softc),
+ a9ptmr_fdt_match, a9ptmr_fdt_attach, NULL, NULL);
+
+static int
+a9ptmr_fdt_match(device_t parent, cfdata_t cf, void *aux)
+{
+ const char * const compatible[] = {
+ "arm,cortex-a9-twd-timer",
+ "arm,cortex-a5-twd-timer",
+ NULL
+ };
+ struct fdt_attach_args * const faa = aux;
+
+ return of_compatible(faa->faa_phandle, compatible) >= 0;
+}
+
+static void
+a9ptmr_fdt_attach(device_t parent, device_t self, void *aux)
+{
+ struct a9ptmr_fdt_softc * const sc = device_private(self);
+ struct fdt_attach_args * const faa = aux;
+ const int phandle = faa->faa_phandle;
+ bus_space_handle_t bsh;
+
+ sc->sc_dev = self;
+ sc->sc_clk = fdtbus_clock_get_index(phandle, 0);
+ if (sc->sc_clk == NULL) {
+ aprint_error(": couldn't get clock\n");
+ return;
+ }
+ if (clk_enable(sc->sc_clk) != 0) {
+ aprint_error(": couldn't enable clock\n");
+ return;
+ }
+
+ uint32_t rate = clk_get_rate(sc->sc_clk);
+ prop_dictionary_t dict = device_properties(self);
+ prop_dictionary_set_uint32(dict, "frequency", rate);
+
+ char intrstr[128];
+ if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
+ aprint_error(": failed to decode interrupt\n");
+ return;
+ }
+
+ aprint_naive("\n");
+ aprint_normal("\n");
+
+ void *ih = fdtbus_intr_establish(phandle, 0, IPL_CLOCK,
+ FDT_INTR_MPSAFE, a9ptmr_intr, NULL);
+ if (ih == NULL) {
+ aprint_error_dev(self, "couldn't install interrupt handler\n");
+ return;
+ }
+ aprint_normal_dev(self, "interrupting on %s\n", intrstr);
+
+ bus_addr_t addr;
+ bus_size_t size;
+ if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
+ aprint_error(": couldn't get registers\n");
+ return;
+ }
+ if (bus_space_map(faa->faa_bst, addr, size, 0, &bsh)) {
+ aprint_error(": couldn't map registers\n");
+ return;
+ }
+
+ struct mpcore_attach_args mpcaa = {
+ .mpcaa_name = "arma9ptmr",
+ .mpcaa_memt = faa->faa_bst,
+ .mpcaa_memh = bsh,
+ .mpcaa_irq = -1,
+ };
+
+ config_found(self, &mpcaa, NULL);
+
+ arm_fdt_cpu_hatch_register(self, a9ptmr_fdt_cpu_hatch);
+ arm_fdt_timer_register(a9ptmr_cpu_initclocks);
+}
+
+static void
+a9ptmr_fdt_cpu_hatch(void *priv, struct cpu_info *ci)
+{
+ a9ptmr_init_cpu_clock(ci);
+}
Index: src/sys/arch/arm/fdt/a9wdt_fdt.c
diff -u /dev/null src/sys/arch/arm/fdt/a9wdt_fdt.c:1.1
--- /dev/null Sat Aug 10 17:03:59 2019
+++ src/sys/arch/arm/fdt/a9wdt_fdt.c Sat Aug 10 17:03:59 2019
@@ -0,0 +1,122 @@
+/* $NetBSD: a9wdt_fdt.c,v 1.1 2019/08/10 17:03:59 skrll Exp $ */
+
+/*-
+ * Copyright (c) 2019 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Nick Hudson
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: a9wdt_fdt.c,v 1.1 2019/08/10 17:03:59 skrll Exp $");
+
+#if 0
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/kmem.h>
+
+#include <arm/cortex/a9tmr_intr.h>
+#include <arm/cortex/mpcore_var.h>
+#include <arm/cortex/a9tmr_var.h>
+#endif
+
+
+#include <sys/param.h>
+#include <sys/bus.h>
+
+#include <arm/cortex/mpcore_var.h>
+
+
+#include <dev/fdt/fdtvar.h>
+#include <arm/fdt/arm_fdtvar.h>
+
+static int a9wdt_fdt_match(device_t, cfdata_t, void *);
+static void a9wdt_fdt_attach(device_t, device_t, void *);
+
+struct a9wdt_fdt_softc {
+ device_t sc_dev;
+ struct clk *sc_clk;
+};
+
+CFATTACH_DECL_NEW(a9wdt_fdt, sizeof(struct a9wdt_fdt_softc),
+ a9wdt_fdt_match, a9wdt_fdt_attach, NULL, NULL);
+
+static int
+a9wdt_fdt_match(device_t parent, cfdata_t cf, void *aux)
+{
+ const char * const compatible[] = {
+ "arm,cortex-a9-twd-wdt",
+ "arm,cortex-a5-twd-wdt",
+ NULL
+ };
+ struct fdt_attach_args * const faa = aux;
+
+ return of_compatible(faa->faa_phandle, compatible) >= 0;
+}
+
+static void
+a9wdt_fdt_attach(device_t parent, device_t self, void *aux)
+{
+ struct a9wdt_fdt_softc * const sc = device_private(self);
+ struct fdt_attach_args * const faa = aux;
+ const int phandle = faa->faa_phandle;
+ bus_space_handle_t bsh;
+
+ sc->sc_dev = self;
+
+ char intrstr[128];
+ if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
+ aprint_error(": failed to decode interrupt\n");
+ return;
+ }
+
+ aprint_naive("\n");
+ aprint_normal("\n");
+
+ bus_addr_t addr;
+ bus_size_t size;
+ if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
+ aprint_error(": couldn't get registers\n");
+ return;
+ }
+ if (bus_space_map(faa->faa_bst, addr, size, 0, &bsh)) {
+ aprint_error(": couldn't map registers\n");
+ return;
+ }
+
+ struct mpcore_attach_args mpcaa = {
+ .mpcaa_name = "a9wdt",
+ .mpcaa_memt = faa->faa_bst,
+ .mpcaa_memh = bsh,
+ .mpcaa_irq = -1,
+ };
+
+ config_found(self, &mpcaa, NULL);
+}
+
