Module Name: src
Committed By: msaitoh
Date: Thu Jan 13 00:21:41 UTC 2022
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Use __BIT(). KNF. No functional change.
To generate a diff of this commit:
cvs rdiff -u -r1.178 -r1.179 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.178 src/sys/arch/x86/include/specialreg.h:1.179
--- src/sys/arch/x86/include/specialreg.h:1.178 Thu Sep 30 15:54:55 2021
+++ src/sys/arch/x86/include/specialreg.h Thu Jan 13 00:21:41 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.178 2021/09/30 15:54:55 msaitoh Exp $ */
+/* $NetBSD: specialreg.h,v 1.179 2022/01/13 00:21:41 msaitoh Exp $ */
/*
* Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -139,12 +139,12 @@
#define XCR0_HDC 0x00002000 /* Hardware Duty Cycle state */
#define XCR0_HWP 0x00010000 /* Hardware P-states */
-#define XCR0_FLAGS1 "\20" \
- "\1" "x87" "\2" "SSE" "\3" "AVX" \
- "\4" "BNDREGS" "\5" "BNDCSR" "\6" "Opmask" \
- "\7" "ZMM_Hi256" "\10" "Hi16_ZMM" "\11" "PT" \
- "\12" "PKRU" "\14" "CET_U" "\15" "CET_S" \
- "\16" "HDC" "\21" "HWP"
+#define XCR0_FLAGS1 "\20" \
+ "\1" "x87" "\2" "SSE" "\3" "AVX" "\4" "BNDREGS" \
+ "\5" "BNDCSR" "\6" "Opmask" "\7" "ZMM_Hi256" "\10" "Hi16_ZMM" \
+ "\11" "PT" "\12" "PKRU" "\14" "CET_U" \
+ "\15" "CET_S" "\16" "HDC" \
+ "\21" "HWP"
/*
* Known FPU bits, only these get enabled. The save area is sized for all the
@@ -205,14 +205,14 @@
#define CPUID_TM 0x20000000 /* thermal monitor (TCC) */
#define CPUID_PBE 0x80000000 /* Pending Break Enable */
-#define CPUID_FLAGS1 "\20" \
- "\1" "FPU" "\2" "VME" "\3" "DE" "\4" "PSE" \
- "\5" "TSC" "\6" "MSR" "\7" "PAE" "\10" "MCE" \
- "\11" "CX8" "\12" "APIC" "\13" "B10" "\14" "SEP" \
- "\15" "MTRR" "\16" "PGE" "\17" "MCA" "\20" "CMOV" \
+#define CPUID_FLAGS1 "\20" \
+ "\1" "FPU" "\2" "VME" "\3" "DE" "\4" "PSE" \
+ "\5" "TSC" "\6" "MSR" "\7" "PAE" "\10" "MCE" \
+ "\11" "CX8" "\12" "APIC" "\13" "B10" "\14" "SEP" \
+ "\15" "MTRR" "\16" "PGE" "\17" "MCA" "\20" "CMOV" \
"\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CLFLUSH" \
- "\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \
- "\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \
+ "\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \
+ "\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \
"\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "PBE"
/* Blacklists of CPUID flags - used to mask certain features */
@@ -259,14 +259,14 @@
#define CPUID2_RDRAND 0x40000000 /* RDRAND (hardware random number) */
#define CPUID2_RAZ 0x80000000 /* RAZ. Indicates guest state. */
-#define CPUID2_FLAGS1 "\20" \
- "\1" "SSE3" "\2" "PCLMULQDQ" "\3" "DTES64" "\4" "MONITOR" \
- "\5" "DS-CPL" "\6" "VMX" "\7" "SMX" "\10" "EST" \
- "\11" "TM2" "\12" "SSSE3" "\13" "CID" "\14" "SDBG" \
- "\15" "FMA" "\16" "CX16" "\17" "xTPR" "\20" "PDCM" \
- "\21" "B16" "\22" "PCID" "\23" "DCA" "\24" "SSE41" \
- "\25" "SSE42" "\26" "X2APIC" "\27" "MOVBE" "\30" "POPCNT" \
- "\31" "DEADLINE" "\32" "AES" "\33" "XSAVE" "\34" "OSXSAVE" \
+#define CPUID2_FLAGS1 "\20" \
+ "\1" "SSE3" "\2" "PCLMULQDQ" "\3" "DTES64" "\4" "MONITOR" \
+ "\5" "DS-CPL" "\6" "VMX" "\7" "SMX" "\10" "EST" \
+ "\11" "TM2" "\12" "SSSE3" "\13" "CID" "\14" "SDBG" \
+ "\15" "FMA" "\16" "CX16" "\17" "xTPR" "\20" "PDCM" \
+ "\21" "B16" "\22" "PCID" "\23" "DCA" "\24" "SSE41" \
+ "\25" "SSE42" "\26" "X2APIC" "\27" "MOVBE" "\30" "POPCNT" \
+ "\31" "DEADLINE" "\32" "AES" "\33" "XSAVE" "\34" "OSXSAVE" \
"\35" "AVX" "\36" "F16C" "\37" "RDRAND" "\40" "RAZ"
/* CPUID Fn00000001 %eax */
@@ -351,19 +351,19 @@
* Intel/AMD Digital Thermal Sensor and
* Power Management, Fn0000_0006 - %eax.
*/
-#define CPUID_DSPM_DTS __BIT(0) /* Digital Thermal Sensor */
-#define CPUID_DSPM_IDA __BIT(1) /* Intel Dynamic Acceleration */
-#define CPUID_DSPM_ARAT __BIT(2) /* Always Running APIC Timer */
-#define CPUID_DSPM_PLN __BIT(4) /* Power Limit Notification */
-#define CPUID_DSPM_ECMD __BIT(5) /* Clock Modulation Extension */
-#define CPUID_DSPM_PTM __BIT(6) /* Package Level Thermal Management */
-#define CPUID_DSPM_HWP __BIT(7) /* HWP */
+#define CPUID_DSPM_DTS __BIT(0) /* Digital Thermal Sensor */
+#define CPUID_DSPM_IDA __BIT(1) /* Intel Dynamic Acceleration */
+#define CPUID_DSPM_ARAT __BIT(2) /* Always Running APIC Timer */
+#define CPUID_DSPM_PLN __BIT(4) /* Power Limit Notification */
+#define CPUID_DSPM_ECMD __BIT(5) /* Clock Modulation Extension */
+#define CPUID_DSPM_PTM __BIT(6) /* Package Level Thermal Management */
+#define CPUID_DSPM_HWP __BIT(7) /* HWP */
#define CPUID_DSPM_HWP_NOTIFY __BIT(8) /* HWP Notification */
-#define CPUID_DSPM_HWP_ACTWIN __BIT(9) /* HWP Activity Window */
-#define CPUID_DSPM_HWP_EPP __BIT(10) /* HWP Energy Performance Preference */
-#define CPUID_DSPM_HWP_PLR __BIT(11) /* HWP Package Level Request */
-#define CPUID_DSPM_HDC __BIT(13) /* Hardware Duty Cycling */
-#define CPUID_DSPM_TBMT3 __BIT(14) /* Turbo Boost Max Technology 3.0 */
+#define CPUID_DSPM_HWP_ACTWIN __BIT(9) /* HWP Activity Window */
+#define CPUID_DSPM_HWP_EPP __BIT(10) /* HWP Energy Performance Preference */
+#define CPUID_DSPM_HWP_PLR __BIT(11) /* HWP Package Level Request */
+#define CPUID_DSPM_HDC __BIT(13) /* Hardware Duty Cycling */
+#define CPUID_DSPM_TBMT3 __BIT(14) /* Turbo Boost Max Technology 3.0 */
#define CPUID_DSPM_HWP_CAP __BIT(15) /* HWP Capabilities */
#define CPUID_DSPM_HWP_PECI __BIT(16) /* HWP PECI override */
#define CPUID_DSPM_HWP_FLEX __BIT(17) /* Flexible HWP */
@@ -371,11 +371,11 @@
#define CPUID_DSPM_HW_FEEDBACK __BIT(19) /* HW_FEEDBACK*, IA32_PACKAGE_TERM* */
#define CPUID_DSPM_HWP_IGNIDL __BIT(20) /* Ignore Idle Logical Processor HWP */
-#define CPUID_DSPM_FLAGS "\20" \
- "\1" "DTS" "\2" "IDA" "\3" "ARAT" \
- "\5" "PLN" "\6" "ECMD" "\7" "PTM" "\10" "HWP" \
+#define CPUID_DSPM_FLAGS "\20" \
+ "\1" "DTS" "\2" "IDA" "\3" "ARAT" \
+ "\5" "PLN" "\6" "ECMD" "\7" "PTM" "\10" "HWP" \
"\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \
- "\16" "HDC" "\17" "TBM3" "\20" "HWP_CAP" \
+ "\16" "HDC" "\17" "TBM3" "\20" "HWP_CAP" \
"\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" "\24HW_FEEDBACK" \
"\25" "HWP_IGNIDL"
@@ -383,8 +383,8 @@
* Intel/AMD Digital Thermal Sensor and
* Power Management, Fn0000_0006 - %ecx.
*/
-#define CPUID_DSPM_HWF 0x00000001 /* MSR_APERF/MSR_MPERF available */
-#define CPUID_DSPM_EPB 0x00000008 /* Energy Performance Bias */
+#define CPUID_DSPM_HWF __BIT(0) /* MSR_APERF/MSR_MPERF available */
+#define CPUID_DSPM_EPB __BIT(3) /* Energy Performance Bias */
#define CPUID_DSPM_FLAGS1 "\20" "\1" "HWF" "\4" "EPB"
@@ -401,47 +401,47 @@
*/
/* %ecx = 0, %ebx */
-#define CPUID_SEF_FSGSBASE __BIT(0) /* {RD,WR}{FS,GS}BASE */
-#define CPUID_SEF_TSC_ADJUST __BIT(1) /* IA32_TSC_ADJUST MSR support */
-#define CPUID_SEF_SGX __BIT(2) /* Software Guard Extensions */
-#define CPUID_SEF_BMI1 __BIT(3) /* advanced bit manipulation ext. 1st grp */
-#define CPUID_SEF_HLE __BIT(4) /* Hardware Lock Elision */
-#define CPUID_SEF_AVX2 __BIT(5) /* Advanced Vector Extensions 2 */
-#define CPUID_SEF_FDPEXONLY __BIT(6) /* x87FPU Data ptr updated only on x87exp */
-#define CPUID_SEF_SMEP __BIT(7) /* Supervisor-Mode Execution Prevention */
-#define CPUID_SEF_BMI2 __BIT(8) /* advanced bit manipulation ext. 2nd grp */
-#define CPUID_SEF_ERMS __BIT(9) /* Enhanced REP MOVSB/STOSB */
-#define CPUID_SEF_INVPCID __BIT(10) /* INVPCID instruction */
-#define CPUID_SEF_RTM __BIT(11) /* Restricted Transactional Memory */
-#define CPUID_SEF_QM __BIT(12) /* Resource Director Technology Monitoring */
-#define CPUID_SEF_FPUCSDS __BIT(13) /* Deprecate FPU CS and FPU DS values */
-#define CPUID_SEF_MPX __BIT(14) /* Memory Protection Extensions */
-#define CPUID_SEF_PQE __BIT(15) /* Resource Director Technology Allocation */
-#define CPUID_SEF_AVX512F __BIT(16) /* AVX-512 Foundation */
-#define CPUID_SEF_AVX512DQ __BIT(17) /* AVX-512 Double/Quadword */
-#define CPUID_SEF_RDSEED __BIT(18) /* RDSEED instruction */
-#define CPUID_SEF_ADX __BIT(19) /* ADCX/ADOX instructions */
-#define CPUID_SEF_SMAP __BIT(20) /* Supervisor-Mode Access Prevention */
-#define CPUID_SEF_AVX512_IFMA __BIT(21) /* AVX-512 Integer Fused Multiply Add */
+#define CPUID_SEF_FSGSBASE __BIT(0) /* {RD,WR}{FS,GS}BASE */
+#define CPUID_SEF_TSC_ADJUST __BIT(1) /* IA32_TSC_ADJUST MSR support */
+#define CPUID_SEF_SGX __BIT(2) /* Software Guard Extensions */
+#define CPUID_SEF_BMI1 __BIT(3) /* advanced bit manipulation ext. 1st grp */
+#define CPUID_SEF_HLE __BIT(4) /* Hardware Lock Elision */
+#define CPUID_SEF_AVX2 __BIT(5) /* Advanced Vector Extensions 2 */
+#define CPUID_SEF_FDPEXONLY __BIT(6) /* x87FPU Data ptr updated only on x87exp */
+#define CPUID_SEF_SMEP __BIT(7) /* Supervisor-Mode Execution Prevention */
+#define CPUID_SEF_BMI2 __BIT(8) /* advanced bit manipulation ext. 2nd grp */
+#define CPUID_SEF_ERMS __BIT(9) /* Enhanced REP MOVSB/STOSB */
+#define CPUID_SEF_INVPCID __BIT(10) /* INVPCID instruction */
+#define CPUID_SEF_RTM __BIT(11) /* Restricted Transactional Memory */
+#define CPUID_SEF_QM __BIT(12) /* Resource Director Technology Monitoring */
+#define CPUID_SEF_FPUCSDS __BIT(13) /* Deprecate FPU CS and FPU DS values */
+#define CPUID_SEF_MPX __BIT(14) /* Memory Protection Extensions */
+#define CPUID_SEF_PQE __BIT(15) /* Resource Director Technology Allocation */
+#define CPUID_SEF_AVX512F __BIT(16) /* AVX-512 Foundation */
+#define CPUID_SEF_AVX512DQ __BIT(17) /* AVX-512 Double/Quadword */
+#define CPUID_SEF_RDSEED __BIT(18) /* RDSEED instruction */
+#define CPUID_SEF_ADX __BIT(19) /* ADCX/ADOX instructions */
+#define CPUID_SEF_SMAP __BIT(20) /* Supervisor-Mode Access Prevention */
+#define CPUID_SEF_AVX512_IFMA __BIT(21) /* AVX-512 Integer Fused Multiply Add */
/* Bit 22 was PCOMMIT */
-#define CPUID_SEF_CLFLUSHOPT __BIT(23) /* Cache Line FLUSH OPTimized */
-#define CPUID_SEF_CLWB __BIT(24) /* Cache Line Write Back */
-#define CPUID_SEF_PT __BIT(25) /* Processor Trace */
-#define CPUID_SEF_AVX512PF __BIT(26) /* AVX-512 PreFetch */
-#define CPUID_SEF_AVX512ER __BIT(27) /* AVX-512 Exponential and Reciprocal */
-#define CPUID_SEF_AVX512CD __BIT(28) /* AVX-512 Conflict Detection */
-#define CPUID_SEF_SHA __BIT(29) /* SHA Extensions */
-#define CPUID_SEF_AVX512BW __BIT(30) /* AVX-512 Byte and Word */
-#define CPUID_SEF_AVX512VL __BIT(31) /* AVX-512 Vector Length */
-
-#define CPUID_SEF_FLAGS "\20" \
- "\1" "FSGSBASE" "\2" "TSCADJUST" "\3" "SGX" "\4" "BMI1" \
- "\5" "HLE" "\6" "AVX2" "\7" "FDPEXONLY" "\10" "SMEP" \
- "\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \
- "\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \
- "\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX" \
+#define CPUID_SEF_CLFLUSHOPT __BIT(23) /* Cache Line FLUSH OPTimized */
+#define CPUID_SEF_CLWB __BIT(24) /* Cache Line Write Back */
+#define CPUID_SEF_PT __BIT(25) /* Processor Trace */
+#define CPUID_SEF_AVX512PF __BIT(26) /* AVX-512 PreFetch */
+#define CPUID_SEF_AVX512ER __BIT(27) /* AVX-512 Exponential and Reciprocal */
+#define CPUID_SEF_AVX512CD __BIT(28) /* AVX-512 Conflict Detection */
+#define CPUID_SEF_SHA __BIT(29) /* SHA Extensions */
+#define CPUID_SEF_AVX512BW __BIT(30) /* AVX-512 Byte and Word */
+#define CPUID_SEF_AVX512VL __BIT(31) /* AVX-512 Vector Length */
+
+#define CPUID_SEF_FLAGS "\20" \
+ "\1" "FSGSBASE" "\2" "TSCADJUST" "\3" "SGX" "\4" "BMI1" \
+ "\5" "HLE" "\6" "AVX2" "\7" "FDPEXONLY" "\10" "SMEP" \
+ "\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \
+ "\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \
+ "\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX" \
"\25" "SMAP" "\26" "AVX512_IFMA" "\30" "CLFLUSHOPT" \
- "\31" "CLWB" "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \
+ "\31" "CLWB" "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \
"\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\40" "AVX512VL"
/* %ecx = 0, %ecx */
@@ -470,14 +470,14 @@
#define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */
#define CPUID_SEF_PKS __BIT(31) /* Protection Keys for Kern-mode pages */
-#define CPUID_SEF_FLAGS1 "\177\20" \
- "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \
- "b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" "b\7CET_SS\0" \
+#define CPUID_SEF_FLAGS1 "\177\20" \
+ "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \
+ "b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" "b\7CET_SS\0" \
"b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\
- "b\14AVX512_BITALG\0" "b\15TME_EN\0" "b\16AVX512_VPOPCNTDQ\0" \
- "b\20LA57\0" \
- "f\21\5MAWAU\0" "b\26RDPID\0" "b\27KL\0" \
- "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \
+ "b\14AVX512_BITALG\0" "b\15TME_EN\0" "b\16AVX512_VPOPCNTDQ\0" \
+ "b\20LA57\0" \
+ "f\21\5MAWAU\0" "b\26RDPID\0" "b\27KL\0" \
+ "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \
"b\34MOVDIR64B\0" "b\36SGXLC\0" "b\37PKS\0"
/* %ecx = 0, %edx */
@@ -500,19 +500,19 @@
#define CPUID_SEF_CORE_CAP __BIT(30) /* IA32_CORE_CAPABILITIES */
#define CPUID_SEF_SSBD __BIT(31) /* Speculative Store Bypass Disable */
-#define CPUID_SEF_FLAGS2 "\20" \
+#define CPUID_SEF_FLAGS2 "\20" \
"\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \
- "\5" "FSREP_MOV" \
- "\11VP2INTERSECT" "\12SRBDS_CTRL" "\13MD_CLEAR" \
- "\16TSX_FORCE_ABORT" "\17SERIALIZE" "\20HYBRID" \
- "\21" "TSXLDTRK" "\23" "PCONFIG" \
- "\25" "CET_IBT" \
- "\33" "IBRS" "\34" "STIBP" \
- "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP" "\40" "SSBD"
+ "\5" "FSREP_MOV" \
+ "\11VP2INTERSECT" "\12SRBDS_CTRL" "\13MD_CLEAR" \
+ "\16TSX_FORCE_ABORT" "\17SERIALIZE" "\20HYBRID" \
+ "\21" "TSXLDTRK" "\23" "PCONFIG" \
+ "\25" "CET_IBT" \
+ "\33" "IBRS" "\34" "STIBP" \
+ "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP" "\40" "SSBD"
/* %ecx = 1, %eax */
#define CPUID_SEF_AVX512_BF16 __BIT(5)
-#define CPUID_SEF1_FLAGS_A "\20" \
+#define CPUID_SEF1_FLAGS_A "\20" \
"\6" "AVX512_BF16"
/*
* Intel CPUID Architectural Performance Monitoring Fn0000000a
@@ -539,14 +539,14 @@
#define CPUID_PERF_BRINSRETR __BIT(5) /* No branch inst. retried */
#define CPUID_PERF_BRMISPRRETR __BIT(6) /* No branch mispredict retry */
-#define CPUID_PERF_FLAGS1 "\177\20" \
+#define CPUID_PERF_FLAGS1 "\177\20" \
"b\0CORECYCL\0" "b\1INSTRETRY\0" "b\2REFCYCL\0" "b\3LLCREF\0" \
"b\4LLCMISS\0" "b\5BRINSRETR\0" "b\6BRMISPRRETR\0"
/* %edx */
#define CPUID_PERF_NFFPC __BITS(4, 0) /* Num of fixed-funct perfcnt */
#define CPUID_PERF_NBWFFPC __BITS(12, 5) /* Bit width of fixed-func pc */
-#define CPUID_PERF_ANYTHREADDEPR __BIT(15) /* Any Thread deprecation */
+#define CPUID_PERF_ANYTHREADDEPR __BIT(15) /* Any Thread deprecation */
#define CPUID_PERF_FLAGS3 "\177\20" \
"f\0\5FixedFunc\0" "f\5\10FFBitwidth\0" "b\17ANYTHREADDEPR\0"
@@ -596,7 +596,7 @@
#define CPUID_PES1_XGETBV 0x00000004 /* xgetbv with ECX = 1 */
#define CPUID_PES1_XSAVES 0x00000008 /* xsaves/xrstors, IA32_XSS */
-#define CPUID_PES1_FLAGS "\20" \
+#define CPUID_PES1_FLAGS "\20" \
"\1" "XSAVEOPT" "\2" "XSAVEC" "\3" "XGETBV" "\4" "XSAVES"
/*
@@ -637,14 +637,14 @@
#define CPUID_RDTSCP 0x08000000 /* Read TSC Pair Instruction */
#define CPUID_EM64T 0x20000000 /* Intel EM64T */
-#define CPUID_INTEL_EXT_FLAGS "\20" \
+#define CPUID_INTEL_EXT_FLAGS "\20" \
"\14" "SYSCALL/SYSRET" "\25" "XD" "\33" "P1GB" \
"\34" "RDTSCP" "\36" "EM64T"
/* Intel Fn80000001 extended features - %ecx */
-#define CPUID_LAHF 0x00000001 /* LAHF/SAHF in IA-32e mode, 64bit sub*/
- /* 0x00000020 */ /* LZCNT. Same as AMD's CPUID_ABM */
-#define CPUID_PREFETCHW 0x00000100 /* PREFETCHW */
+#define CPUID_LAHF __BIT(0) /* LAHF/SAHF in IA-32e mode, 64bit sub*/
+ /* __BIT(5) */ /* LZCNT. Same as AMD's CPUID_ABM */
+#define CPUID_PREFETCHW __BIT(8) /* PREFETCHW */
#define CPUID_INTEL_FLAGS4 "\20" \
"\1" "LAHF" "\02" "B01" "\03" "B02" \
@@ -666,7 +666,7 @@
#define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */
#define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */
-#define CPUID_EXT_FLAGS "\20" \
+#define CPUID_EXT_FLAGS "\20" \
"\14" "SYSCALL/SYSRET" \
"\24" "MPC" \
"\25" "NOX" "\27" "MMXX" "\30" "MMX" \
@@ -675,42 +675,42 @@
/* AMD Fn8000_0001 extended features - %ecx */
/* CPUID_LAHF LAHF/SAHF instruction */
-#define CPUID_CMPLEGACY 0x00000002 /* Compare Legacy */
-#define CPUID_SVM 0x00000004 /* Secure Virtual Machine */
-#define CPUID_EAPIC 0x00000008 /* Extended APIC space */
-#define CPUID_ALTMOVCR0 0x00000010 /* Lock Mov Cr0 */
-#define CPUID_ABM 0x00000020 /* LZCNT instruction */
-#define CPUID_SSE4A 0x00000040 /* SSE4A instruction set */
-#define CPUID_MISALIGNSSE 0x00000080 /* Misaligned SSE */
-#define CPUID_3DNOWPF 0x00000100 /* 3DNow Prefetch */
-#define CPUID_OSVW 0x00000200 /* OS visible workarounds */
-#define CPUID_IBS 0x00000400 /* Instruction Based Sampling */
-#define CPUID_XOP 0x00000800 /* XOP instruction set */
-#define CPUID_SKINIT 0x00001000 /* SKINIT */
-#define CPUID_WDT 0x00002000 /* watchdog timer support */
-#define CPUID_LWP 0x00008000 /* Light Weight Profiling */
-#define CPUID_FMA4 0x00010000 /* FMA4 instructions */
-#define CPUID_TCE 0x00020000 /* Translation cache Extension */
-#define CPUID_NODEID 0x00080000 /* NodeID MSR available*/
-#define CPUID_TBM 0x00200000 /* TBM instructions */
-#define CPUID_TOPOEXT 0x00400000 /* cpuid Topology Extension */
-#define CPUID_PCEC 0x00800000 /* Perf Ctr Ext Core */
-#define CPUID_PCENB 0x01000000 /* Perf Ctr Ext NB */
-#define CPUID_SPM 0x02000000 /* Stream Perf Mon */
-#define CPUID_DBE 0x04000000 /* Data Breakpoint Extension */
-#define CPUID_PTSC 0x08000000 /* PerfTsc */
-#define CPUID_L2IPERFC 0x10000000 /* L2I performance counter Extension */
-#define CPUID_MWAITX 0x20000000 /* MWAITX/MONITORX support */
+#define CPUID_CMPLEGACY __BIT(1) /* Compare Legacy */
+#define CPUID_SVM __BIT(2) /* Secure Virtual Machine */
+#define CPUID_EAPIC __BIT(3) /* Extended APIC space */
+#define CPUID_ALTMOVCR0 __BIT(4) /* Lock Mov Cr0 */
+#define CPUID_ABM __BIT(5) /* LZCNT instruction */
+#define CPUID_SSE4A __BIT(6) /* SSE4A instruction set */
+#define CPUID_MISALIGNSSE __BIT(7) /* Misaligned SSE */
+#define CPUID_3DNOWPF __BIT(8) /* 3DNow Prefetch */
+#define CPUID_OSVW __BIT(9) /* OS visible workarounds */
+#define CPUID_IBS __BIT(10) /* Instruction Based Sampling */
+#define CPUID_XOP __BIT(11) /* XOP instruction set */
+#define CPUID_SKINIT __BIT(12) /* SKINIT */
+#define CPUID_WDT __BIT(13) /* watchdog timer support */
+#define CPUID_LWP __BIT(15) /* Light Weight Profiling */
+#define CPUID_FMA4 __BIT(16) /* FMA4 instructions */
+#define CPUID_TCE __BIT(17) /* Translation cache Extension */
+#define CPUID_NODEID __BIT(19) /* NodeID MSR available */
+#define CPUID_TBM __BIT(21) /* TBM instructions */
+#define CPUID_TOPOEXT __BIT(22) /* cpuid Topology Extension */
+#define CPUID_PCEC __BIT(23) /* Perf Ctr Ext Core */
+#define CPUID_PCENB __BIT(24) /* Perf Ctr Ext NB */
+#define CPUID_SPM __BIT(25) /* Stream Perf Mon */
+#define CPUID_DBE __BIT(26) /* Data Breakpoint Extension */
+#define CPUID_PTSC __BIT(27) /* PerfTsc */
+#define CPUID_L2IPERFC __BIT(28) /* L2I performance counter Extension */
+#define CPUID_MWAITX __BIT(29) /* MWAITX/MONITORX support */
-#define CPUID_AMD_FLAGS4 "\20" \
- "\1" "LAHF" "\2" "CMPLEGACY" "\3" "SVM" "\4" "EAPIC" \
+#define CPUID_AMD_FLAGS4 "\20" \
+ "\1" "LAHF" "\2" "CMPLEGACY" "\3" "SVM" "\4" "EAPIC" \
"\5" "ALTMOVCR0" "\6" "LZCNT" "\7" "SSE4A" "\10" "MISALIGNSSE" \
- "\11" "3DNOWPREFETCH" \
- "\12" "OSVW" "\13" "IBS" "\14" "XOP" \
- "\15" "SKINIT" "\16" "WDT" "\17" "B14" "\20" "LWP" \
- "\21" "FMA4" "\22" "TCE" "\23" "B18" "\24" "NodeID" \
- "\25" "B20" "\26" "TBM" "\27" "TopoExt" "\30" "PCExtC" \
- "\31" "PCExtNB" "\32" "StrmPM" "\33" "DBExt" "\34" "PerfTsc" \
+ "\11" "3DNOWPREFETCH" \
+ "\12" "OSVW" "\13" "IBS" "\14" "XOP" \
+ "\15" "SKINIT" "\16" "WDT" "\17" "B14" "\20" "LWP" \
+ "\21" "FMA4" "\22" "TCE" "\23" "B18" "\24" "NodeID" \
+ "\25" "B20" "\26" "TBM" "\27" "TopoExt" "\30" "PCExtC" \
+ "\31" "PCExtNB" "\32" "StrmPM" "\33" "DBExt" "\34" "PerfTsc" \
"\35" "L2IPERFC" "\36" "MWAITX" "\37" "B30" "\40" "B31"
/*
@@ -719,21 +719,21 @@
*
* Only ITSC is for both Intel and AMD. Others are only for AMD.
*/
-#define CPUID_APM_TS 0x00000001 /* Temperature Sensor */
-#define CPUID_APM_FID 0x00000002 /* Frequency ID control */
-#define CPUID_APM_VID 0x00000004 /* Voltage ID control */
-#define CPUID_APM_TTP 0x00000008 /* THERMTRIP (PCI F3xE4 register) */
-#define CPUID_APM_HTC 0x00000010 /* Hardware thermal control (HTC) */
-#define CPUID_APM_STC 0x00000020 /* Software thermal control (STC) */
-#define CPUID_APM_100 0x00000040 /* 100MHz multiplier control */
-#define CPUID_APM_HWP 0x00000080 /* HW P-State control */
-#define CPUID_APM_ITSC 0x00000100 /* invariant TSC */
-#define CPUID_APM_CPB 0x00000200 /* Core performance boost */
-#define CPUID_APM_EFF 0x00000400 /* Effective Frequency (read-only) */
-#define CPUID_APM_PROCFI 0x00000800 /* Proc Feedback Interface */
-#define CPUID_APM_PROCPR 0x00001000 /* Proc Power Reporting */
-#define CPUID_APM_CONNSTBY 0x00002000 /* Connected Standby */
-#define CPUID_APM_RAPL 0x00004000 /* Running Average Power Limit */
+#define CPUID_APM_TS __BIT(0) /* Temperature Sensor */
+#define CPUID_APM_FID __BIT(1) /* Frequency ID control */
+#define CPUID_APM_VID __BIT(2) /* Voltage ID control */
+#define CPUID_APM_TTP __BIT(3) /* THERMTRIP (PCI F3xE4 register) */
+#define CPUID_APM_HTC __BIT(4) /* Hardware thermal control (HTC) */
+#define CPUID_APM_STC __BIT(5) /* Software thermal control (STC) */
+#define CPUID_APM_100 __BIT(6) /* 100MHz multiplier control */
+#define CPUID_APM_HWP __BIT(7) /* HW P-State control */
+#define CPUID_APM_ITSC __BIT(8) /* invariant TSC */
+#define CPUID_APM_CPB __BIT(9) /* Core performance boost */
+#define CPUID_APM_EFF __BIT(10) /* Effective Frequency (read-only) */
+#define CPUID_APM_PROCFI __BIT(11) /* Proc Feedback Interface */
+#define CPUID_APM_PROCPR __BIT(12) /* Proc Power Reporting */
+#define CPUID_APM_CONNSTBY __BIT(13) /* Connected Standby */
+#define CPUID_APM_RAPL __BIT(14) /* Running Average Power Limit */
#define CPUID_APM_FLAGS "\20" \
"\1" "TS" "\2" "FID" "\3" "VID" "\4" "TTP" \
@@ -864,7 +864,7 @@
#define CPUID_VIA_HAS_PMM 0x00001000 /* RSA Instructions */
#define CPUID_VIA_DO_PMM 0x00002000
-#define CPUID_FLAGS_PADLOCK "\20" \
+#define CPUID_FLAGS_PADLOCK "\20" \
"\3" "RNG" "\7" "AES" "\11" "AES/CTR" "\13" "SHA1/SHA256" \
"\15" "RSA"
