Module Name: src
Committed By: msaitoh
Date: Sat Jan 15 10:09:15 UTC 2022
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Whitespace. No functional change.
To generate a diff of this commit:
cvs rdiff -u -r1.184 -r1.185 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.184 src/sys/arch/x86/include/specialreg.h:1.185
--- src/sys/arch/x86/include/specialreg.h:1.184 Sat Jan 15 09:58:23 2022
+++ src/sys/arch/x86/include/specialreg.h Sat Jan 15 10:09:15 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.184 2022/01/15 09:58:23 msaitoh Exp $ */
+/* $NetBSD: specialreg.h,v 1.185 2022/01/15 10:09:15 msaitoh Exp $ */
/*
* Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -781,28 +781,28 @@
*/
/* %ebx */
-#define CPUID_CAPEX_CLZERO __BIT(0) /* CLZERO instruction */
-#define CPUID_CAPEX_IRPERF __BIT(1) /* InstRetCntMsr */
-#define CPUID_CAPEX_XSAVEERPTR __BIT(2) /* RstrFpErrPtrs by XRSTOR */
-#define CPUID_CAPEX_RDPRU __BIT(4) /* RDPRU instruction */
-#define CPUID_CAPEX_MCOMMIT __BIT(8) /* MCOMMIT instruction */
-#define CPUID_CAPEX_WBNOINVD __BIT(9) /* WBNOINVD instruction */
-#define CPUID_CAPEX_IBPB __BIT(12) /* Speculation Control IBPB */
-#define CPUID_CAPEX_IBRS __BIT(14) /* Speculation Control IBRS */
-#define CPUID_CAPEX_STIBP __BIT(15) /* Speculation Control STIBP */
-#define CPUID_CAPEX_IBRS_ALWAYSON __BIT(16) /* IBRS always on mode */
-#define CPUID_CAPEX_STIBP_ALWAYSON __BIT(17) /* STIBP always on mode */
-#define CPUID_CAPEX_PREFER_IBRS __BIT(18) /* IBRS preferred */
-#define CPUID_CAPEX_SSBD __BIT(24) /* Speculation Control SSBD */
-#define CPUID_CAPEX_VIRT_SSBD __BIT(25) /* Virt Spec Control SSBD */
-#define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */
-
-#define CPUID_CAPEX_FLAGS "\20" \
- "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" \
- "\5RDPRU" "\7B6" \
- "\11MCOMMIT" "\12WBNOINVD" "\13B10" \
- "\15IBPB" "\16B13" "\17IBRS" "\20STIBP" \
- "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" "\24B19" \
+#define CPUID_CAPEX_CLZERO __BIT(0) /* CLZERO instruction */
+#define CPUID_CAPEX_IRPERF __BIT(1) /* InstRetCntMsr */
+#define CPUID_CAPEX_XSAVEERPTR __BIT(2) /* RstrFpErrPtrs by XRSTOR */
+#define CPUID_CAPEX_RDPRU __BIT(4) /* RDPRU instruction */
+#define CPUID_CAPEX_MCOMMIT __BIT(8) /* MCOMMIT instruction */
+#define CPUID_CAPEX_WBNOINVD __BIT(9) /* WBNOINVD instruction */
+#define CPUID_CAPEX_IBPB __BIT(12) /* Speculation Control IBPB */
+#define CPUID_CAPEX_IBRS __BIT(14) /* Speculation Control IBRS */
+#define CPUID_CAPEX_STIBP __BIT(15) /* Speculation Control STIBP */
+#define CPUID_CAPEX_IBRS_ALWAYSON __BIT(16) /* IBRS always on mode */
+#define CPUID_CAPEX_STIBP_ALWAYSON __BIT(17) /* STIBP always on mode */
+#define CPUID_CAPEX_PREFER_IBRS __BIT(18) /* IBRS preferred */
+#define CPUID_CAPEX_SSBD __BIT(24) /* Speculation Control SSBD */
+#define CPUID_CAPEX_VIRT_SSBD __BIT(25) /* Virt Spec Control SSBD */
+#define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */
+
+#define CPUID_CAPEX_FLAGS "\20" \
+ "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" \
+ "\5RDPRU" "\7B6" \
+ "\11MCOMMIT" "\12WBNOINVD" "\13B10" \
+ "\15IBPB" "\16B13" "\17IBRS" "\20STIBP" \
+ "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" "\24B19" \
"\31SSBD" "\32VIRT_SSBD" "\33SSB_NO"
/* %ecx */
