Module Name: src
Committed By: thorpej
Date: Wed Jul 20 15:45:28 UTC 2022
Modified Files:
src/sys/arch/alpha/include: tc_machdep.h
src/sys/dev/tc: pxg.c stic.c
Log Message:
In the Alpha tc_syncbus(), we need to issue a MB because WMB does not
order reads with respect to writes. Remove now-redundant tc_wmb()
calls before tc_syncbus().
NFC on MIPS other than removing a redundant wbflush() (tc_wmb() followed
by tc_syncbus()).
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/alpha/include/tc_machdep.h
cvs rdiff -u -r1.36 -r1.37 src/sys/dev/tc/pxg.c
cvs rdiff -u -r1.58 -r1.59 src/sys/dev/tc/stic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/alpha/include/tc_machdep.h
diff -u src/sys/arch/alpha/include/tc_machdep.h:1.7 src/sys/arch/alpha/include/tc_machdep.h:1.8
--- src/sys/arch/alpha/include/tc_machdep.h:1.7 Thu Jun 22 16:46:52 2017
+++ src/sys/arch/alpha/include/tc_machdep.h Wed Jul 20 15:45:28 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: tc_machdep.h,v 1.7 2017/06/22 16:46:52 flxd Exp $ */
+/* $NetBSD: tc_machdep.h,v 1.8 2022/07/20 15:45:28 thorpej Exp $ */
/*
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
@@ -71,6 +71,11 @@ typedef int32_t tc_offset_t;
#define tc_syncbus() \
do { \
volatile uint32_t no_optimize; \
+ /* \
+ * WMB does not order reads with respect to writes, so a \
+ * MB is required here. \
+ */ \
+ alpha_mb(); \
no_optimize = \
*(volatile uint32_t *)ALPHA_PHYS_TO_K0SEG(0x00000001f0080220); \
__USE(no_optimize); \
Index: src/sys/dev/tc/pxg.c
diff -u src/sys/dev/tc/pxg.c:1.36 src/sys/dev/tc/pxg.c:1.37
--- src/sys/dev/tc/pxg.c:1.36 Sun Nov 10 21:16:37 2019
+++ src/sys/dev/tc/pxg.c Wed Jul 20 15:45:28 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: pxg.c,v 1.36 2019/11/10 21:16:37 chs Exp $ */
+/* $NetBSD: pxg.c,v 1.37 2022/07/20 15:45:28 thorpej Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pxg.c,v 1.36 2019/11/10 21:16:37 chs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pxg.c,v 1.37 2022/07/20 15:45:28 thorpej Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -164,7 +164,6 @@ pxg_attach(device_t parent, device_t sel
/* Start the i860. */
si->si_slotbase[PXG_I860_START_OFFSET >> 2] = 1;
- tc_wmb();
tc_syncbus();
DELAY(40000);
#endif
@@ -208,7 +207,6 @@ pxg_init(struct stic_info *si)
slot[PXG_I860_RESET_OFFSET >> 2] = 0;
tc_wmb();
slot[PXG_HOST_INTR_OFFSET >> 2] = 0;
- tc_wmb();
tc_syncbus();
DELAY(40000);
Index: src/sys/dev/tc/stic.c
diff -u src/sys/dev/tc/stic.c:1.58 src/sys/dev/tc/stic.c:1.59
--- src/sys/dev/tc/stic.c:1.58 Wed May 18 13:56:32 2022
+++ src/sys/dev/tc/stic.c Wed Jul 20 15:45:28 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: stic.c,v 1.58 2022/05/18 13:56:32 andvar Exp $ */
+/* $NetBSD: stic.c,v 1.59 2022/07/20 15:45:28 thorpej Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001 The NetBSD Foundation, Inc.
@@ -36,7 +36,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: stic.c,v 1.58 2022/05/18 13:56:32 andvar Exp $");
+__KERNEL_RCSID(0, "$NetBSD: stic.c,v 1.59 2022/07/20 15:45:28 thorpej Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -288,7 +288,6 @@ stic_init(struct stic_info *si)
/* Now reset the VDAC. */
*si->si_vdac_reset = 0;
- tc_wmb();
tc_syncbus();
DELAY(1000);
@@ -358,13 +357,11 @@ stic_reset(struct stic_info *si)
* Initialize the interface chip registers.
*/
sr->sr_sticsr = 0x00000030; /* Get the STIC's attention. */
- tc_wmb();
tc_syncbus();
DELAY(2000); /* wait 2ms for STIC to respond. */
sr->sr_sticsr = 0x00000000; /* Hit the STIC's csr again... */
tc_wmb();
sr->sr_buscsr = 0xffffffff; /* and bash its bus-access csr. */
- tc_wmb();
tc_syncbus(); /* Blam! */
DELAY(20000); /* wait until the stic recovers... */
@@ -402,7 +399,6 @@ stic_reset(struct stic_info *si)
sr->sr_ipdvint =
STIC_INT_WE | STIC_INT_P | STIC_INT_E_EN | STIC_INT_V_EN;
sr->sr_sticsr = 8;
- tc_wmb();
tc_syncbus();
}
