Module Name: src
Committed By: andvar
Date: Thu Jul 21 10:09:21 UTC 2022
Modified Files:
src/sys/arch/arm/at91: at91aic.c
src/sys/arch/arm/ixp12x0: ixp12x0_com.c
src/sys/arch/hpcarm/dev: ipaq_lcdreg.h
src/sys/arch/hpcmips/tx: tx39icu.c
src/sys/arch/hpcmips/vr: rtc.c vrc4173bcu.c vrpmu.c
src/sys/arch/ia64/include: dig64.h
src/sys/dev/marvell: gtpci.c
Log Message:
fix typos in comments and log messages, mainly s/intrrupt/interrupt/.
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/at91/at91aic.c
cvs rdiff -u -r1.49 -r1.50 src/sys/arch/arm/ixp12x0/ixp12x0_com.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/hpcarm/dev/ipaq_lcdreg.h
cvs rdiff -u -r1.37 -r1.38 src/sys/arch/hpcmips/tx/tx39icu.c
cvs rdiff -u -r1.35 -r1.36 src/sys/arch/hpcmips/vr/rtc.c
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/hpcmips/vr/vrc4173bcu.c
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/hpcmips/vr/vrpmu.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/ia64/include/dig64.h
cvs rdiff -u -r1.36 -r1.37 src/sys/dev/marvell/gtpci.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/at91/at91aic.c
diff -u src/sys/arch/arm/at91/at91aic.c:1.12 src/sys/arch/arm/at91/at91aic.c:1.13
--- src/sys/arch/arm/at91/at91aic.c:1.12 Fri Nov 20 18:03:52 2020
+++ src/sys/arch/arm/at91/at91aic.c Thu Jul 21 10:09:20 2022
@@ -1,5 +1,5 @@
-/* $Id: at91aic.c,v 1.12 2020/11/20 18:03:52 thorpej Exp $ */
-/* $NetBSD: at91aic.c,v 1.12 2020/11/20 18:03:52 thorpej Exp $ */
+/* $Id: at91aic.c,v 1.13 2022/07/21 10:09:20 andvar Exp $ */
+/* $NetBSD: at91aic.c,v 1.13 2022/07/21 10:09:20 andvar Exp $ */
/*
* Copyright (c) 2007 Embedtronics Oy.
@@ -244,7 +244,7 @@ at91aic_init(void)
aic_intr_enabled = 0;
- // disable intrrupts:
+ // disable interrupts:
AICREG(AIC_IDCR) = -1;
for (i = 0; i < NIRQ; i++) {
Index: src/sys/arch/arm/ixp12x0/ixp12x0_com.c
diff -u src/sys/arch/arm/ixp12x0/ixp12x0_com.c:1.49 src/sys/arch/arm/ixp12x0/ixp12x0_com.c:1.50
--- src/sys/arch/arm/ixp12x0/ixp12x0_com.c:1.49 Fri Nov 20 18:26:26 2020
+++ src/sys/arch/arm/ixp12x0/ixp12x0_com.c Thu Jul 21 10:09:20 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: ixp12x0_com.c,v 1.49 2020/11/20 18:26:26 thorpej Exp $ */
+/* $NetBSD: ixp12x0_com.c,v 1.50 2022/07/21 10:09:20 andvar Exp $ */
/*
* Copyright (c) 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -66,7 +66,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ixp12x0_com.c,v 1.49 2020/11/20 18:26:26 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ixp12x0_com.c,v 1.50 2022/07/21 10:09:20 andvar Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
@@ -122,7 +122,7 @@ void ixpcomcnprobe(struct con
void ixpcomcninit(struct consdev *);
uint32_t ixpcom_cr = 0; /* tell cr to *_intr.c */
-uint32_t ixpcom_imask = 0; /* intrrupt mask from *_intr.c */
+uint32_t ixpcom_imask = 0; /* interrupt mask from *_intr.c */
static struct ixpcom_cons_softc {
Index: src/sys/arch/hpcarm/dev/ipaq_lcdreg.h
diff -u src/sys/arch/hpcarm/dev/ipaq_lcdreg.h:1.2 src/sys/arch/hpcarm/dev/ipaq_lcdreg.h:1.3
--- src/sys/arch/hpcarm/dev/ipaq_lcdreg.h:1.2 Mon Apr 28 20:23:21 2008
+++ src/sys/arch/hpcarm/dev/ipaq_lcdreg.h Thu Jul 21 10:09:20 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: ipaq_lcdreg.h,v 1.2 2008/04/28 20:23:21 martin Exp $ */
+/* $NetBSD: ipaq_lcdreg.h,v 1.3 2022/07/21 10:09:20 andvar Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -41,10 +41,10 @@
#define CR0_LEN (1<<0) /* LCD enable */
#define CR0_CMS (1<<1) /* color op enable */
#define CR0_SDS (1<<2) /* Single display or Double display */
-#define CR0_LDM (1<<3) /* LDD status bit ignore(dont intrrupt) */
+#define CR0_LDM (1<<3) /* LDD status bit ignore (don't interrupt) */
#define CR0_BAM (1<<4) /* Base address update does not
- generate an intrrupt */
-#define CR0_ERM (1<<5) /* Bus error generate an intrrupt */
+ generate an interrupt */
+#define CR0_ERM (1<<5) /* Bus error generate an interrupt */
#define CR0_PAS (1<<7) /* Passive / Active and TFT-LCD enable */
#define CR0_BLE (1<<8) /* endian select 0=little */
#define CR0_DPD (1<<9)
Index: src/sys/arch/hpcmips/tx/tx39icu.c
diff -u src/sys/arch/hpcmips/tx/tx39icu.c:1.37 src/sys/arch/hpcmips/tx/tx39icu.c:1.38
--- src/sys/arch/hpcmips/tx/tx39icu.c:1.37 Sat Nov 21 21:23:48 2020
+++ src/sys/arch/hpcmips/tx/tx39icu.c Thu Jul 21 10:09:21 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: tx39icu.c,v 1.37 2020/11/21 21:23:48 thorpej Exp $ */
+/* $NetBSD: tx39icu.c,v 1.38 2022/07/21 10:09:21 andvar Exp $ */
/*-
* Copyright (c) 1999-2001 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tx39icu.c,v 1.37 2020/11/21 21:23:48 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tx39icu.c,v 1.38 2022/07/21 10:09:21 andvar Exp $");
#include "opt_vr41xx.h"
#include "opt_tx39xx.h"
@@ -489,7 +489,7 @@ tx39_intr_decode(int intr, int *set, int
|| intr == 6
#endif /* TX392X */
) {
- panic("tx39icu_decode: bogus intrrupt line. %d", intr);
+ panic("tx39icu_decode: bogus interrupt line. %d", intr);
}
*set = intr / 32;
*bit = intr % 32;
Index: src/sys/arch/hpcmips/vr/rtc.c
diff -u src/sys/arch/hpcmips/vr/rtc.c:1.35 src/sys/arch/hpcmips/vr/rtc.c:1.36
--- src/sys/arch/hpcmips/vr/rtc.c:1.35 Sat Jul 11 10:32:45 2015
+++ src/sys/arch/hpcmips/vr/rtc.c Thu Jul 21 10:09:21 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: rtc.c,v 1.35 2015/07/11 10:32:45 kamil Exp $ */
+/* $NetBSD: rtc.c,v 1.36 2022/07/21 10:09:21 andvar Exp $ */
/*-
* Copyright (c) 1999 Shin Takemura. All rights reserved.
@@ -36,7 +36,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rtc.c,v 1.35 2015/07/11 10:32:45 kamil Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rtc.c,v 1.36 2022/07/21 10:09:21 andvar Exp $");
#include "opt_vr41xx.h"
@@ -193,7 +193,7 @@ vrrtc_attach(device_t parent, device_t s
bus_space_write_2(sc->sc_iot, sc->sc_ioh, TCLK_L_REG_W, 0);
}
/*
- * Clear all rtc intrrupts.
+ * Clear all rtc interrupts.
*/
bus_space_write_2(sc->sc_iot, sc->sc_ioh, RTCINT_REG_W, RTCINT_ALL);
Index: src/sys/arch/hpcmips/vr/vrc4173bcu.c
diff -u src/sys/arch/hpcmips/vr/vrc4173bcu.c:1.26 src/sys/arch/hpcmips/vr/vrc4173bcu.c:1.27
--- src/sys/arch/hpcmips/vr/vrc4173bcu.c:1.26 Sat Aug 7 16:18:54 2021
+++ src/sys/arch/hpcmips/vr/vrc4173bcu.c Thu Jul 21 10:09:21 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: vrc4173bcu.c,v 1.26 2021/08/07 16:18:54 thorpej Exp $ */
+/* $NetBSD: vrc4173bcu.c,v 1.27 2022/07/21 10:09:21 andvar Exp $ */
/*-
* Copyright (c) 2001,2002 Enami Tsugutomo.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: vrc4173bcu.c,v 1.26 2021/08/07 16:18:54 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: vrc4173bcu.c,v 1.27 2022/07/21 10:09:21 andvar Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -97,21 +97,21 @@ static struct vrc4173bcu_platdep {
{
&platid_mask_MACH_VICTOR_INTERLINK_MPC303,
USE_WINCE_CLKMASK, /* clock mask */
- (1 << VRC4173ICU_USBINTR)| /* intrrupts */
+ (1 << VRC4173ICU_USBINTR)| /* interrupts */
(1 << VRC4173ICU_PCMCIA1INTR)|
(1 << VRC4173ICU_PCMCIA2INTR),
},
{
&platid_mask_MACH_VICTOR_INTERLINK_MPC304,
USE_WINCE_CLKMASK, /* clock mask */
- (1 << VRC4173ICU_USBINTR)| /* intrrupts */
+ (1 << VRC4173ICU_USBINTR)| /* interrupts */
(1 << VRC4173ICU_PCMCIA1INTR)|
(1 << VRC4173ICU_PCMCIA2INTR),
},
{
&platid_mask_MACH_NEC_MCR_SIGMARION2,
USE_WINCE_CLKMASK, /* clock mask */
- (1 << VRC4173ICU_USBINTR), /* intrrupts */
+ (1 << VRC4173ICU_USBINTR), /* interrupts */
},
{
&platid_wild,
Index: src/sys/arch/hpcmips/vr/vrpmu.c
diff -u src/sys/arch/hpcmips/vr/vrpmu.c:1.20 src/sys/arch/hpcmips/vr/vrpmu.c:1.21
--- src/sys/arch/hpcmips/vr/vrpmu.c:1.20 Wed Mar 26 17:53:36 2014
+++ src/sys/arch/hpcmips/vr/vrpmu.c Thu Jul 21 10:09:21 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: vrpmu.c,v 1.20 2014/03/26 17:53:36 christos Exp $ */
+/* $NetBSD: vrpmu.c,v 1.21 2022/07/21 10:09:21 andvar Exp $ */
/*
* Copyright (c) 1999 M. Warner Losh. All rights reserved.
@@ -28,7 +28,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: vrpmu.c,v 1.20 2014/03/26 17:53:36 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: vrpmu.c,v 1.21 2022/07/21 10:09:21 andvar Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -136,7 +136,7 @@ vrpmuattach(device_t parent, device_t se
}
printf("\n");
- /* dump current intrrupt states */
+ /* dump current interrupt states */
vrpmu_dump_intr(sc);
DDUMP_REGS(DEBUG_BOOT, sc);
/* clear interrupt status */
Index: src/sys/arch/ia64/include/dig64.h
diff -u src/sys/arch/ia64/include/dig64.h:1.2 src/sys/arch/ia64/include/dig64.h:1.3
--- src/sys/arch/ia64/include/dig64.h:1.2 Mon Jul 20 04:41:37 2009
+++ src/sys/arch/ia64/include/dig64.h Thu Jul 21 10:09:21 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: dig64.h,v 1.2 2009/07/20 04:41:37 kiyohara Exp $ */
+/* $NetBSD: dig64.h,v 1.3 2022/07/21 10:09:21 andvar Exp $ */
/*-
* Copyright (c) 2002 Marcel Moolenaar
@@ -32,7 +32,7 @@
#define _MACHINE_DIG64_H_
/*
- * This header file written refer to 'DIG64 Desriptions for Primary Console &
+ * This header file written refer to 'DIG64 Descriptions for Primary Console &
* Debug Port Devices'.
*/
@@ -109,7 +109,7 @@ struct dig64_vga_spec {
#define DIG64_FLAGS_TRANS_SPARSE (1 << 3) /* Sparse Transration */
#define DIG64_FLAGS_TYPE_STATIC (0 << 4) /* Type Static */
#define DIG64_FLAGS_TYPE_TRANS (1 << 4) /* Type Translation */
-#define DIG64_FLAGS_INTR_SUPP (1 << 6) /* Intrrupt supported */
+#define DIG64_FLAGS_INTR_SUPP (1 << 6) /* Interrupt supported */
#define DIG64_FLAGS_MMIO_TRA_VALID (1 << 8)
#define DIG64_FLAGS_IOPORT_TRA_VALID (1 << 9)
Index: src/sys/dev/marvell/gtpci.c
diff -u src/sys/dev/marvell/gtpci.c:1.36 src/sys/dev/marvell/gtpci.c:1.37
--- src/sys/dev/marvell/gtpci.c:1.36 Sat Aug 7 16:19:13 2021
+++ src/sys/dev/marvell/gtpci.c Thu Jul 21 10:09:21 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: gtpci.c,v 1.36 2021/08/07 16:19:13 thorpej Exp $ */
+/* $NetBSD: gtpci.c,v 1.37 2022/07/21 10:09:21 andvar Exp $ */
/*
* Copyright (c) 2008, 2009 KIYOHARA Takashi
* All rights reserved.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gtpci.c,v 1.36 2021/08/07 16:19:13 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtpci.c,v 1.37 2022/07/21 10:09:21 andvar Exp $");
#include "opt_pci.h"
#include "pci.h"
@@ -207,7 +207,7 @@ gtpci_attach(device_t parent, device_t s
aprint_error_dev(self, "int2gpp not an array\n");
return;
}
- aprint_normal_dev(self, "use intrrupt pin:");
+ aprint_normal_dev(self, "use interrupt pin:");
for (intr = PCI_INTERRUPT_PIN_A;
intr <= PCI_INTERRUPT_PIN_D &&
intr < prop_array_count(int2gpp);
