Module Name: src
Committed By: skrll
Date: Sat Oct 15 16:20:32 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Remove unnecessary register assignments
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/riscv/riscv/locore.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/locore.S
diff -u src/sys/arch/riscv/riscv/locore.S:1.31 src/sys/arch/riscv/riscv/locore.S:1.32
--- src/sys/arch/riscv/riscv/locore.S:1.31 Fri Oct 14 08:10:22 2022
+++ src/sys/arch/riscv/riscv/locore.S Sat Oct 15 16:20:32 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.31 2022/10/14 08:10:22 skrll Exp $ */
+/* $NetBSD: locore.S,v 1.32 2022/10/15 16:20:32 skrll Exp $ */
/*-
* Copyright (c) 2014, 2022 The NetBSD Foundation, Inc.
@@ -125,9 +125,6 @@ ENTRY_NP(start)
* an initial PDETAB.
*/
- li s10, PAGE_SIZE
- li s9, USPACE
-
PTR_LA s5, _C_LABEL(lwp0uspace)
PTR_LA s6, _C_LABEL(bootstk)
