CVS commit: src/sys/arch/arm/xilinx

[Jared D. McNeill]

Module Name:    src
Committed By:   jmcneill
Date:           Sat Nov  5 17:28:55 UTC 2022

Modified Files:
        src/sys/arch/arm/xilinx: zynq7000_clkc.c

Log Message:
Add I2C clocks


To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/xilinx/zynq7000_clkc.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.


Modified files:

Index: src/sys/arch/arm/xilinx/zynq7000_clkc.c
diff -u src/sys/arch/arm/xilinx/zynq7000_clkc.c:1.3 src/sys/arch/arm/xilinx/zynq7000_clkc.c:1.4
--- src/sys/arch/arm/xilinx/zynq7000_clkc.c:1.3	Wed Oct 26 22:14:22 2022
+++ src/sys/arch/arm/xilinx/zynq7000_clkc.c	Sat Nov  5 17:28:55 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: zynq7000_clkc.c,v 1.3 2022/10/26 22:14:22 jmcneill Exp $ */
+/* $NetBSD: zynq7000_clkc.c,v 1.4 2022/11/05 17:28:55 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2022 Jared McNeill <jmcne...@invisible.ca>
@@ -28,7 +28,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(0, "$NetBSD: zynq7000_clkc.c,v 1.3 2022/10/26 22:14:22 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: zynq7000_clkc.c,v 1.4 2022/11/05 17:28:55 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -56,6 +56,8 @@ __KERNEL_RCSID(0, "$NetBSD: zynq7000_clk
 #define	APER_CLK_CTRL	0x12c
 #define	 UART1_CPU_1XCLKACT	__BIT(21)
 #define	 UART0_CPU_1XCLKACT	__BIT(20)
+#define	 I2C1_CPU_1XCLKACT	__BIT(19)
+#define	 I2C0_CPU_1XCLKACT	__BIT(18)
 #define	 SDI1_CPU_1XCLKACT	__BIT(11)
 #define	 SDI0_CPU_1XCLKACT	__BIT(10)
 #define	SDIO_CLK_CTRL	0x150
@@ -246,7 +248,9 @@ zynq7000_clkc_clk_get_rate(void *priv, s
 		   clk == &sc->sc_clk[clkid_uart1]) {
 		return zynq7000_clkc_get_rate_iop(sc, UART_CLK_CTRL);
 	} else if (clk == &sc->sc_clk[clkid_uart0_aper] ||
-		   clk == &sc->sc_clk[clkid_uart1_aper]) {
+		   clk == &sc->sc_clk[clkid_uart1_aper] ||
+		   clk == &sc->sc_clk[clkid_i2c0_aper] ||
+		   clk == &sc->sc_clk[clkid_i2c1_aper]) {
 		return zynq7000_clkc_clk_get_rate(sc,
 		    &sc->sc_clk[clkid_cpu_1x]);
 	} else {
@@ -298,6 +302,12 @@ zynq7000_clkc_clk_enable(void *priv, str
 	} else if (clk == &sc->sc_clk[clkid_uart1_aper]) {
 		reg = APER_CLK_CTRL;
 		mask = UART1_CPU_1XCLKACT;
+	} else if (clk == &sc->sc_clk[clkid_i2c0_aper]) {
+		reg = APER_CLK_CTRL;
+		mask = I2C0_CPU_1XCLKACT;
+	} else if (clk == &sc->sc_clk[clkid_i2c1_aper]) {
+		reg = APER_CLK_CTRL;
+		mask = I2C1_CPU_1XCLKACT;
 	} else {
 		return ENXIO;
 	}