Module Name: src
Committed By: skrll
Date: Tue Nov 8 12:48:28 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
whitepsace nit
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/riscv/include/sysreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/sysreg.h
diff -u src/sys/arch/riscv/include/sysreg.h:1.18 src/sys/arch/riscv/include/sysreg.h:1.19
--- src/sys/arch/riscv/include/sysreg.h:1.18 Sat Oct 15 06:53:49 2022
+++ src/sys/arch/riscv/include/sysreg.h Tue Nov 8 12:48:28 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: sysreg.h,v 1.18 2022/10/15 06:53:49 skrll Exp $ */
+/* $NetBSD: sysreg.h,v 1.19 2022/11/08 12:48:28 skrll Exp $ */
/*
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -144,7 +144,7 @@ riscvreg_fcsr_write_frm(uint32_t __new)
/* Supervisor interrupt registers */
/* ... interrupt pending register (sip) */
- /* Bit (XLEN-1)-10 is WIRI */
+ /* Bit (XLEN-1) - 10 is WIRI */
#define SIP_SEIP __BIT(9)
#define SIP_UEIP __BIT(8)
/* Bit 7-6 is WIRI */
