Module Name: src
Committed By: simonb
Date: Tue Nov 8 13:47:09 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Parentheses police.
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/riscv/include/sysreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/sysreg.h
diff -u src/sys/arch/riscv/include/sysreg.h:1.20 src/sys/arch/riscv/include/sysreg.h:1.21
--- src/sys/arch/riscv/include/sysreg.h:1.20 Tue Nov 8 13:35:32 2022
+++ src/sys/arch/riscv/include/sysreg.h Tue Nov 8 13:47:09 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: sysreg.h,v 1.20 2022/11/08 13:35:32 simonb Exp $ */
+/* $NetBSD: sysreg.h,v 1.21 2022/11/08 13:47:09 simonb Exp $ */
/*
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -210,8 +210,8 @@ riscvreg_status_set(uint32_t __mask)
}
// Cause register
-#define CAUSE_INTERRUPT_P(cause) ((cause) & __BIT(XLEN-1)))
-#define CAUSE_CODE(cause) ((cause) & __BITS((XLEN-2), 0))
+#define CAUSE_INTERRUPT_P(cause) ((cause) & __BIT(XLEN-1))
+#define CAUSE_CODE(cause) ((cause) & __BITS(XLEN-2, 0))
// Cause register - exceptions
#define CAUSE_FETCH_MISALIGNED 0
