Module Name: src
Committed By: andvar
Date: Sat May 6 22:17:28 UTC 2023
Modified Files:
src/sys/arch/arm/at91: at91pioreg.h
src/sys/arch/arm/s3c2xx0: s3c2440_i2s.c
src/sys/arch/hppa/dev: viper.h
src/sys/arch/sparc64/include: ctlreg.h
src/sys/dev/cardbus: cardbusreg.h
src/sys/dev/ic: cd18xxreg.h
src/sys/dev/pci: pccbbreg.h
Log Message:
few more typos in the word "register", mainly s/resister/register/.
In one comment I assume that it was meant to be pull-up resistor.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/at91/at91pioreg.h
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/s3c2xx0/s3c2440_i2s.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/hppa/dev/viper.h
cvs rdiff -u -r1.67 -r1.68 src/sys/arch/sparc64/include/ctlreg.h
cvs rdiff -u -r1.7 -r1.8 src/sys/dev/cardbus/cardbusreg.h
cvs rdiff -u -r1.5 -r1.6 src/sys/dev/ic/cd18xxreg.h
cvs rdiff -u -r1.16 -r1.17 src/sys/dev/pci/pccbbreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/at91/at91pioreg.h
diff -u src/sys/arch/arm/at91/at91pioreg.h:1.2 src/sys/arch/arm/at91/at91pioreg.h:1.3
--- src/sys/arch/arm/at91/at91pioreg.h:1.2 Thu Jul 3 01:15:38 2008
+++ src/sys/arch/arm/at91/at91pioreg.h Sat May 6 22:17:28 2023
@@ -1,5 +1,5 @@
-/* $Id: at91pioreg.h,v 1.2 2008/07/03 01:15:38 matt Exp $ */
-/* $NetBSD: at91pioreg.h,v 1.2 2008/07/03 01:15:38 matt Exp $ */
+/* $Id: at91pioreg.h,v 1.3 2023/05/06 22:17:28 andvar Exp $ */
+/* $NetBSD: at91pioreg.h,v 1.3 2023/05/06 22:17:28 andvar Exp $ */
/*
* Copyright (c) 2007 Embedtronics Oy. All rights reserved.
@@ -58,6 +58,6 @@
#define PIO_OWER 0xA0U /* A0: PIO Output Write Enable */
#define PIO_OWDR 0xA4U /* A4: PIO Output Write Disable */
#define PIO_OWSR 0xA8U /* A8: PIO Output Write Status Reg */
-#define PIO_VERSION 0xFCU /* FC: version reqister (AT91SAM92xx) */
+#define PIO_VERSION 0xFCU /* FC: version register (AT91SAM92xx) */
#endif /* _AT91GPIOREG_H_ */
Index: src/sys/arch/arm/s3c2xx0/s3c2440_i2s.c
diff -u src/sys/arch/arm/s3c2xx0/s3c2440_i2s.c:1.7 src/sys/arch/arm/s3c2xx0/s3c2440_i2s.c:1.8
--- src/sys/arch/arm/s3c2xx0/s3c2440_i2s.c:1.7 Tue Sep 27 06:36:43 2022
+++ src/sys/arch/arm/s3c2xx0/s3c2440_i2s.c Sat May 6 22:17:28 2023
@@ -156,7 +156,7 @@ s3c2440_i2s_init(struct s3c2440_i2s_soft
reg = GPIO_SET_FUNC(reg, 4, 2);
bus_space_write_4(sc->sc_iot, sc->sc_gpio_ioh, GPIO_PECON, reg);
- /* Disable Pull-up resister for all I2S pins */
+ /* Disable Pull-up resistor for all I2S pins */
reg = bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, GPIO_PEUP);
reg = GPIO_SET_DATA(reg, 0, 1);
Index: src/sys/arch/hppa/dev/viper.h
diff -u src/sys/arch/hppa/dev/viper.h:1.2 src/sys/arch/hppa/dev/viper.h:1.3
--- src/sys/arch/hppa/dev/viper.h:1.2 Sat Oct 18 08:33:25 2014
+++ src/sys/arch/hppa/dev/viper.h Sat May 6 22:17:28 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: viper.h,v 1.2 2014/10/18 08:33:25 snj Exp $ */
+/* $NetBSD: viper.h,v 1.3 2023/05/06 22:17:28 andvar Exp $ */
/* $OpenBSD: viper.h,v 1.2 1999/06/29 20:56:10 mickey Exp $ */
@@ -144,7 +144,7 @@ struct vi_trs {
/*
** Viper also creates HPA registers for the graphics accelerator (Venom).
-** Venom has two sets of resisters; the User HPA contains registers that
+** Venom has two sets of registers; the User HPA contains registers that
** users are allowed to access, while the Supervisor HPA is only accessible
** by code running at the most priviliged level. Both sets of registers
** are defined below.
Index: src/sys/arch/sparc64/include/ctlreg.h
diff -u src/sys/arch/sparc64/include/ctlreg.h:1.67 src/sys/arch/sparc64/include/ctlreg.h:1.68
--- src/sys/arch/sparc64/include/ctlreg.h:1.67 Wed Nov 13 10:06:38 2019
+++ src/sys/arch/sparc64/include/ctlreg.h Sat May 6 22:17:28 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: ctlreg.h,v 1.67 2019/11/13 10:06:38 nakayama Exp $ */
+/* $NetBSD: ctlreg.h,v 1.68 2023/05/06 22:17:28 andvar Exp $ */
/*
* Copyright (c) 1996-2002 Eduardo Horvath
@@ -396,7 +396,7 @@
* Interrupt registers. This really gets hairy.
*/
-/* IRSR -- Interrupt Receive Status Ragister */
+/* IRSR -- Interrupt Receive Status Register */
#define ASI_IRSR 0x49
#define IRSR 0x00
#define IRSR_BUSY 0x020
Index: src/sys/dev/cardbus/cardbusreg.h
diff -u src/sys/dev/cardbus/cardbusreg.h:1.7 src/sys/dev/cardbus/cardbusreg.h:1.8
--- src/sys/dev/cardbus/cardbusreg.h:1.7 Mon Aug 1 11:20:27 2011
+++ src/sys/dev/cardbus/cardbusreg.h Sat May 6 22:17:28 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: cardbusreg.h,v 1.7 2011/08/01 11:20:27 drochner Exp $ */
+/* $NetBSD: cardbusreg.h,v 1.8 2023/05/06 22:17:28 andvar Exp $ */
/*
* Copyright (c) 2001
@@ -31,7 +31,7 @@
#include <dev/pci/pcivar.h> /* for pcitag_t */
-/* Base Resisters */
+/* Base Registers */
#define CARDBUS_CIS_REG 0x28
#define CARDBUS_ROM_REG 0x30
# define CARDBUS_CIS_ASIMASK 0x07
Index: src/sys/dev/ic/cd18xxreg.h
diff -u src/sys/dev/ic/cd18xxreg.h:1.5 src/sys/dev/ic/cd18xxreg.h:1.6
--- src/sys/dev/ic/cd18xxreg.h:1.5 Fri Dec 30 20:25:56 2022
+++ src/sys/dev/ic/cd18xxreg.h Sat May 6 22:17:28 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: cd18xxreg.h,v 1.5 2022/12/30 20:25:56 andvar Exp $ */
+/* $NetBSD: cd18xxreg.h,v 1.6 2023/05/06 22:17:28 andvar Exp $ */
/*
* Copyright (c) 1998, 2001 Matthew R. Green
@@ -259,7 +259,7 @@
#define CD18xx_RBR_RxD 0x40 /* last RxD input */
#define CD18xx_RBR_STARTHUNT 0x20 /* hunting for a start bit */
-/* bit rate period resisters */
+/* bit rate period registers */
#define CD18xx_xBRPR_TPC 0x10 /* ticks per character */
/* mode change register */
Index: src/sys/dev/pci/pccbbreg.h
diff -u src/sys/dev/pci/pccbbreg.h:1.16 src/sys/dev/pci/pccbbreg.h:1.17
--- src/sys/dev/pci/pccbbreg.h:1.16 Tue Oct 15 18:20:44 2019
+++ src/sys/dev/pci/pccbbreg.h Sat May 6 22:17:28 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: pccbbreg.h,v 1.16 2019/10/15 18:20:44 msaitoh Exp $ */
+/* $NetBSD: pccbbreg.h,v 1.17 2023/05/06 22:17:28 andvar Exp $ */
/*
* Copyright (c) 1999 HAYAKAWA Koichi. All rights reserved.
@@ -147,7 +147,7 @@
/*
- * Special resister definition for Toshiba ToPIC95/97
+ * Special register definition for Toshiba ToPIC95/97
* These values are borrowed from pcmcia-cs/Linux.
*/
#define TOPIC_SOCKET_CTRL 0x90
