Module Name: src
Committed By: martin
Date: Wed Jun 21 19:04:19 UTC 2023
Modified Files:
src/sys/arch/x86/include [netbsd-9]: specialreg.h
src/usr.sbin/cpuctl/arch [netbsd-9]: i386.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #1646):
sys/arch/x86/include/specialreg.h: revision 1.202
sys/arch/x86/include/specialreg.h: revision 1.203
usr.sbin/cpuctl/arch/i386.c: revision 1.136
Add some CPUID bits from PPR for AMD Family 19h Model 61h Revision B1.
Add AMD CPUID Fn0000_0008 %ebx bit 3 INVLPGB.
To generate a diff of this commit:
cvs rdiff -u -r1.150.2.12 -r1.150.2.13 src/sys/arch/x86/include/specialreg.h
cvs rdiff -u -r1.104.2.12 -r1.104.2.13 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.150.2.12 src/sys/arch/x86/include/specialreg.h:1.150.2.13
--- src/sys/arch/x86/include/specialreg.h:1.150.2.12 Mon Jan 23 13:00:53 2023
+++ src/sys/arch/x86/include/specialreg.h Wed Jun 21 19:04:19 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.150.2.12 2023/01/23 13:00:53 martin Exp $ */
+/* $NetBSD: specialreg.h,v 1.150.2.13 2023/06/21 19:04:19 martin Exp $ */
/*
* Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -868,6 +868,7 @@
#define CPUID_CAPEX_CLZERO __BIT(0) /* CLZERO instruction */
#define CPUID_CAPEX_IRPERF __BIT(1) /* InstRetCntMsr */
#define CPUID_CAPEX_XSAVEERPTR __BIT(2) /* RstrFpErrPtrs by XRSTOR */
+#define CPUID_CAPEX_INVLPGB __BIT(3) /* INVLPGB instruction */
#define CPUID_CAPEX_RDPRU __BIT(4) /* RDPRU instruction */
#define CPUID_CAPEX_MBE __BIT(6) /* Memory Bandwidth Enforcement */
#define CPUID_CAPEX_MCOMMIT __BIT(8) /* MCOMMIT instruction */
@@ -890,7 +891,7 @@
#define CPUID_CAPEX_BTC_NO __BIT(29) /* Branch Type Confusion NO */
#define CPUID_CAPEX_FLAGS "\20" \
- "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" \
+ "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" "\4INVLPGB" \
"\5RDPRU" "\7MBE" \
"\11MCOMMIT" "\12WBNOINVD" "\13B10" \
"\15IBPB" "\16INT_WBINVD" "\17IBRS" "\20STIBP" \
@@ -936,6 +937,9 @@
#define CPUID_AMD_SVM_TLBICTL __BIT(24) /* TLB Intercept Control */
#define CPUID_AMD_SVM_VNMI __BIT(25) /* NMI Virtualization */
#define CPUID_AMD_SVM_IBSVIRT __BIT(26) /* IBS Virtualization */
+#define CPUID_AMD_SVM_XLVTOFFFLTCHG __BIT(27) /* Ext LVToffset FLT changed */
+#define CPUID_AMD_SVM_VMCBADRCHKCHG __BIT(28) /* VMCB addr check changed */
+
#define CPUID_AMD_SVM_FLAGS "\20" \
"\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \
@@ -946,8 +950,8 @@
"\20" "V_VMSAVE_VMLOAD" \
"\21" "VGIF" "\22" "GMET" "\23x2AVIC" "\24SSSCHECK" \
"\25" "SPEC_CTRL" "\26" "ROGPT" "\30HOST_MCE_OVERRIDE" \
- "\31" "TLBICTL" "\32VNMI" "\33IBSVIRT" "\34B27" \
- "\35B28"
+ "\31" "TLBICTL" "\32VNMI" "\33IBSVIRT" "\34ExtLvtOffsetFaultChg" \
+ "\35VmcbAddrChkChg"
/*
* AMD Instruction-Based Sampling Capabilities.
@@ -1050,21 +1054,26 @@
/* %eax */
#define CPUID_AMDEXT2_NONESTEDDBP __BIT(0) /* No nested data breakpoints */
+#define CPUID_AMDEXT2_FGKBNOSERIAL __BIT(1) /* {FS,GS,K}BASE WRMSR !serializ */
#define CPUID_AMDEXT2_LFENCESERIAL __BIT(2) /* LFENCE always serializing */
#define CPUID_AMDEXT2_SMMPGCFGLCK __BIT(3) /* SMM Paging configuration lock */
#define CPUID_AMDEXT2_NULLSELCLRB __BIT(6) /* Null segment selector clr base */
#define CPUID_AMDEXT2_UPADDRIGN __BIT(7) /* Upper Address Ignore */
#define CPUID_AMDEXT2_AUTOIBRS __BIT(8) /* Automatic IBRS */
#define CPUID_AMDEXT2_NOSMMCTL __BIT(9) /* SMM_CTL MSR is not supported */
+#define CPUID_AMDEXT2_FSRS __BIT(10) /* Fast Short Rep Stosb */
+#define CPUID_AMDEXT2_FSRC __BIT(11) /* Fast Short Rep Cmpsb */
#define CPUID_AMDEXT2_PREFETCHCTL __BIT(13) /* Prefetch control MSR */
#define CPUID_AMDEXT2_CPUIDUSRDIS __BIT(17) /* CPUID dis. for non-priv. soft */
+#define CPUID_AMDEXT2_EPSF __BIT(18) /* Enhanced Predective Store Fwd */
#define CPUID_AMDEXT2_FLAGS "\20" \
- "\1NoNestedDataBp" "\3LfenceAlwaysSerialize" "\4SmmPgCfgLock" \
+ "\1NoNestedDataBp" "\2FsGsKernelGsBaseNonSerializing" \
+ "\3LfenceAlwaysSerialize" "\4SmmPgCfgLock" \
"\7NullSelectClearsBase" "\10UpperAddressIgnore" \
- "\11AutomaticIBRS" "\12NoSmmCtlMSR" \
+ "\11AutomaticIBRS" "\12NoSmmCtlMSR" "\13FSRS" "\14FSRC" \
"\16PrefetchCtlMSR" \
- "\22CpuidUserDis"
+ "\22CpuidUserDis" "\23EPSF"
/*
* AMD Extended Performance Monitoring and Debug
@@ -1082,7 +1091,8 @@
/* %ebx */
#define CPUID_AXPERF_NCPC __BITS(3, 0) /* Num of Core PMC counters */
#define CPUID_AXPERF_NLBRSTACK __BITS(9, 4) /* Num of LBR Stack entries */
-#define CPUID_AXPERF_NNBPC __BITS(15, 10) /* Num of Northbridge PMC */
+#define CPUID_AXPERF_NNBPC __BITS(15, 10) /* Num of NorthBridge PMCs */
+#define CPUID_AXPERF_NUMCPC __BITS(21, 16) /* Num of UMC PMCs */
/*
* Centaur Extended Feature flags.
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.104.2.12 src/usr.sbin/cpuctl/arch/i386.c:1.104.2.13
--- src/usr.sbin/cpuctl/arch/i386.c:1.104.2.12 Mon Jan 23 13:04:11 2023
+++ src/usr.sbin/cpuctl/arch/i386.c Wed Jun 21 19:04:19 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.104.2.12 2023/01/23 13:04:11 martin Exp $ */
+/* $NetBSD: i386.c,v 1.104.2.13 2023/06/21 19:04:19 martin Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include <sys/cdefs.h>
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.104.2.12 2023/01/23 13:04:11 martin Exp $");
+__RCSID("$NetBSD: i386.c,v 1.104.2.13 2023/06/21 19:04:19 martin Exp $");
#endif /* not lint */
#include <sys/types.h>
@@ -2274,7 +2274,7 @@ identifycpu(int fd, const char *cpuname)
CPUID_AMD_ENCMEM_FLAGS, descs[0]);
}
if (ci->ci_max_ext_cpuid >= 0x80000022) {
- uint8_t ncore, nnb, nlbrs;
+ uint8_t ncore, nnb, numc, nlbrs;
x86_cpuid(0x80000022, descs);
print_bits(cpuname, "Perfmon:",
@@ -2282,10 +2282,11 @@ identifycpu(int fd, const char *cpuname)
ncore = __SHIFTOUT(descs[1], CPUID_AXPERF_NCPC);
nnb = __SHIFTOUT(descs[1], CPUID_AXPERF_NNBPC);
+ numc = __SHIFTOUT(descs[1], CPUID_AXPERF_NUMCPC);
nlbrs = __SHIFTOUT(descs[1], CPUID_AXPERF_NLBRSTACK);
aprint_verbose("%s: Perfmon: counters: "
- "Core %hhu, Northbridge %hhu\n", cpuname,
- ncore, nnb);
+ "Core %hhu, Northbridge %hhu, UMC %hhu\n", cpuname,
+ ncore, nnb, numc);
aprint_verbose("%s: Perfmon: LBR Stack %hhu entries\n",
cpuname, nlbrs);
}
