Module Name: src
Committed By: msaitoh
Date: Tue Jul 14 00:00:44 UTC 2009
Modified Files:
src/sys/dev/pci: if_wm.c if_wmreg.h
Log Message:
Some fixes for i80003 and ICH{8,9,10) from e1000 driver and document:
Add setting for KABGTXD register for ICH{8,9,10}.
ICH9 and ICH10 has no FCAL, FCAH and FCT like ICH8.
Add special setting for FCTTV and TCTL_EXT register for i80003
The special setting fopr TIPG is only for i80003.
Some of kumeran settings are only for i80003's bugs.
Add some ICH10 fixes.
To generate a diff of this commit:
cvs rdiff -u -r1.176 -r1.177 src/sys/dev/pci/if_wm.c
cvs rdiff -u -r1.27 -r1.28 src/sys/dev/pci/if_wmreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/if_wm.c
diff -u src/sys/dev/pci/if_wm.c:1.176 src/sys/dev/pci/if_wm.c:1.177
--- src/sys/dev/pci/if_wm.c:1.176 Mon Jul 13 23:31:19 2009
+++ src/sys/dev/pci/if_wm.c Tue Jul 14 00:00:44 2009
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wm.c,v 1.176 2009/07/13 23:31:19 msaitoh Exp $ */
+/* $NetBSD: if_wm.c,v 1.177 2009/07/14 00:00:44 msaitoh Exp $ */
/*
* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@@ -76,7 +76,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.176 2009/07/13 23:31:19 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.177 2009/07/14 00:00:44 msaitoh Exp $");
#include "bpfilter.h"
#include "rnd.h"
@@ -3264,7 +3264,8 @@
*
* XXX Values could probably stand some tuning.
*/
- if (sc->sc_type != WM_T_ICH8) {
+ if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9)
+ && (sc->sc_type != WM_T_ICH10)) {
CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST);
CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST);
CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL);
@@ -3278,7 +3279,11 @@
CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT);
CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl);
}
- CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT);
+
+ if (sc->sc_type == WM_T_80003)
+ CSR_WRITE(sc, WMREG_FCTTV, 0xffff);
+ else
+ CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT);
/* Deal with VLAN enables. */
if (VLAN_ATTACHED(&sc->sc_ethercom))
@@ -3288,29 +3293,47 @@
/* Write the control registers. */
CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
- if (sc->sc_type >= WM_T_80003 && (sc->sc_flags & WM_F_HAS_MII)) {
+
+ if (sc->sc_flags & WM_F_HAS_MII) {
int val;
- val = CSR_READ(sc, WMREG_CTRL_EXT);
- val &= ~CTRL_EXT_LINK_MODE_MASK;
- CSR_WRITE(sc, WMREG_CTRL_EXT, val);
-
- /* Bypass RX and TX FIFO's */
- wm_kmrn_i80003_writereg(sc, KUMCTRLSTA_OFFSET_FIFO_CTRL,
- KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
- KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
+
+ switch (sc->sc_type) {
+ case WM_T_80003:
+ case WM_T_ICH8:
+ case WM_T_ICH9:
+ case WM_T_ICH10:
+ /*
+ * Set the mac to wait the maximum time between each
+ * iteration and increase the max iterations when
+ * polling the phy; this fixes erroneous timeouts at
+ * 10Mbps.
+ */
+ wm_kmrn_i80003_writereg(sc, KUMCTRLSTA_OFFSET_TIMEOUTS,
+ 0xFFFF);
+ val = wm_kmrn_i80003_readreg(sc,
+ KUMCTRLSTA_OFFSET_INB_PARAM);
+ val |= 0x3F;
+ wm_kmrn_i80003_writereg(sc,
+ KUMCTRLSTA_OFFSET_INB_PARAM, val);
+ break;
+ default:
+ break;
+ }
+
+ if (sc->sc_type == WM_T_80003) {
+ val = CSR_READ(sc, WMREG_CTRL_EXT);
+ val &= ~CTRL_EXT_LINK_MODE_MASK;
+ CSR_WRITE(sc, WMREG_CTRL_EXT, val);
+
+ /* Bypass RX and TX FIFO's */
+ wm_kmrn_i80003_writereg(sc, KUMCTRLSTA_OFFSET_FIFO_CTRL,
+ KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
+ KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
- wm_kmrn_i80003_writereg(sc, KUMCTRLSTA_OFFSET_INB_CTRL,
- KUMCTRLSTA_INB_CTRL_DIS_PADDING |
- KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT);
- /*
- * Set the mac to wait the maximum time between each
- * iteration and increase the max iterations when
- * polling the phy; this fixes erroneous timeouts at 10Mbps.
- */
- wm_kmrn_i80003_writereg(sc, KUMCTRLSTA_OFFSET_TIMEOUTS, 0xFFFF);
- val = wm_kmrn_i80003_readreg(sc, KUMCTRLSTA_OFFSET_INB_PARAM);
- val |= 0x3F;
- wm_kmrn_i80003_writereg(sc, KUMCTRLSTA_OFFSET_INB_PARAM, val);
+ wm_kmrn_i80003_writereg(sc, KUMCTRLSTA_OFFSET_INB_CTRL,
+ KUMCTRLSTA_INB_CTRL_DIS_PADDING |
+ KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT);
+ }
}
#if 0
CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
@@ -3342,6 +3365,13 @@
sc->sc_icr |= ICR_RXCFG;
CSR_WRITE(sc, WMREG_IMS, sc->sc_icr);
+ if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
+ || (sc->sc_type == WM_T_ICH10)) {
+ reg = CSR_READ(sc, WMREG_KABGTXD);
+ reg |= KABGTXD_BGSQLBIAS;
+ CSR_WRITE(sc, WMREG_KABGTXD, reg);
+ }
+
/* Set up the inter-packet gap. */
CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg);
@@ -3385,6 +3415,13 @@
sc->sc_tctl |= TCTL_RTLC;
CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
+ if (sc->sc_type == WM_T_80003) {
+ reg = CSR_READ(sc, WMREG_TCTL_EXT);
+ reg &= ~TCTL_EXT_GCEX_MASK;
+ reg |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
+ CSR_WRITE(sc, WMREG_TCTL_EXT, reg);
+ }
+
/* Set the media. */
if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0)
goto out;
@@ -4487,7 +4524,7 @@
/* We have MII. */
sc->sc_flags |= WM_F_HAS_MII;
- if (sc->sc_type >= WM_T_80003)
+ if (sc->sc_type == WM_T_80003)
sc->sc_tipg = TIPG_1000T_80003_DFLT;
else
sc->sc_tipg = TIPG_1000T_DFLT;
Index: src/sys/dev/pci/if_wmreg.h
diff -u src/sys/dev/pci/if_wmreg.h:1.27 src/sys/dev/pci/if_wmreg.h:1.28
--- src/sys/dev/pci/if_wmreg.h:1.27 Tue Apr 7 18:23:37 2009
+++ src/sys/dev/pci/if_wmreg.h Tue Jul 14 00:00:44 2009
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wmreg.h,v 1.27 2009/04/07 18:23:37 msaitoh Exp $ */
+/* $NetBSD: if_wmreg.h,v 1.28 2009/07/14 00:00:44 msaitoh Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -610,8 +610,14 @@
#define WMREG_TXDMAC 0x3000 /* Transfer DMA Control */
#define TXDMAC_DPP (1U << 0) /* disable packet prefetch */
+#define WMREG_KABGTXD 0x3004 /* AFE and Gap Transmit Ref Data */
+#define KABGTXD_BGSQLBIAS 0x00050000
+
#define WMREG_TSPMT 0x3830 /* TCP Segmentation Pad and Minimum
Threshold (Cordova) */
+
+#define WMREG_TARC0 0x3840 /* Tx arbitration count */
+
#define TSPMT_TSMT(x) (x) /* TCP seg min transfer */
#define TSPMT_TSPBP(x) ((x) << 16) /* TCP seg pkt buf padding */
