Module Name: src
Committed By: cliff
Date: Tue Sep 15 02:34:34 UTC 2009
Modified Files:
src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixlreg.h
Log Message:
add som XLS PIC register defines
To generate a diff of this commit:
cvs rdiff -u -r1.1.2.1 -r1.1.2.2 src/sys/arch/mips/rmi/rmixlreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/rmi/rmixlreg.h
diff -u src/sys/arch/mips/rmi/rmixlreg.h:1.1.2.1 src/sys/arch/mips/rmi/rmixlreg.h:1.1.2.2
--- src/sys/arch/mips/rmi/rmixlreg.h:1.1.2.1 Sun Sep 13 03:27:38 2009
+++ src/sys/arch/mips/rmi/rmixlreg.h Tue Sep 15 02:34:34 2009
@@ -1,4 +1,4 @@
-/* $NetBSD: rmixlreg.h,v 1.1.2.1 2009/09/13 03:27:38 cliff Exp $ */
+/* $NetBSD: rmixlreg.h,v 1.1.2.2 2009/09/15 02:34:34 cliff Exp $ */
/*-
* Copyright (c) 2009 The NetBSD Foundation, Inc.
@@ -216,5 +216,26 @@
#define RMIXL_PIC_IPIBASE_ID_RESb __BITS(19,18)
#define RMIXL_PIC_IPIBASE_ID_THREAD __BITS(22,20) /* Thread ID */
+/*
+ * RMIXL_PIC_IRTENTRYC0 bits
+ * IRT Entry low word
+ */
+#define RMIXL_PIC_IRTENTRYC0_TMASK __BITS(7,0) /* Thread Mask */
+#define RMIXL_PIC_IRTENTRYC0_RESV __BITS(31,8)
+
+/*
+ * RMIXL_PIC_IRTENTRYC1 bits
+ * IRT Entry high word
+ */
+#define RMIXL_PIC_IRTENTRYC1_INTVEC __BITS(5,0) /* maps to bit# in CPU's EIRR */
+#define RMIXL_PIC_IRTENTRYC1_GL __BIT(6) /* 0=Global; 1=Local */
+#define RMIXL_PIC_IRTENTRYC1_NMI __BIT(7) /* 0=Maskable; 1=NMI */
+#define RMIXL_PIC_IRTENTRYC1_RESV __BITS(28,8)
+#define RMIXL_PIC_IRTENTRYC1_P __BIT(29) /* 0=Rising/High; 1=Falling/Low */
+#define RMIXL_PIC_IRTENTRYC1_TRG __BIT(30) /* 0=Edge; 1=Level */
+#define RMIXL_PIC_IRTENTRYC1_VALID __BIT(31) /* 0=Invalid; 1=Valid IRT Entry */
+
+
+
#endif /* _MIPS_RMI_RMIRMIXLEGS_H_ */
