Module Name: src Committed By: tsutsui Date: Sat Sep 19 11:53:42 UTC 2009
Modified Files: src/sys/dev/sbus: bereg.h qe.c qec.c qecreg.h qereg.h Log Message: u_intNN_t -> uintNN_t To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/dev/sbus/bereg.h cvs rdiff -u -r1.54 -r1.55 src/sys/dev/sbus/qe.c cvs rdiff -u -r1.49 -r1.50 src/sys/dev/sbus/qec.c cvs rdiff -u -r1.3 -r1.4 src/sys/dev/sbus/qecreg.h cvs rdiff -u -r1.6 -r1.7 src/sys/dev/sbus/qereg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/dev/sbus/bereg.h diff -u src/sys/dev/sbus/bereg.h:1.8 src/sys/dev/sbus/bereg.h:1.9 --- src/sys/dev/sbus/bereg.h:1.8 Mon Apr 28 20:23:57 2008 +++ src/sys/dev/sbus/bereg.h Sat Sep 19 11:53:42 2009 @@ -1,4 +1,4 @@ -/* $NetBSD: bereg.h,v 1.8 2008/04/28 20:23:57 martin Exp $ */ +/* $NetBSD: bereg.h,v 1.9 2009/09/19 11:53:42 tsutsui Exp $ */ /*- * Copyright (c) 1999 The NetBSD Foundation, Inc. @@ -61,54 +61,54 @@ */ #if 0 struct be_bregs { - u_int32_t xif_cfg; /* XIF config */ - u_int32_t _unused[63]; /* reserved */ - u_int32_t stat; /* status, clear on read */ - u_int32_t imask; /* interrupt mask */ - u_int32_t _unused2[64]; /* reserved */ - u_int32_t tx_swreset; /* tx software reset */ - u_int32_t tx_cfg; /* tx config */ - u_int32_t ipkt_gap1; /* inter-packet gap 1 */ - u_int32_t ipkt_gap2; /* inter-packet gap 2 */ - u_int32_t attempt_limit; /* tx attempt limit */ - u_int32_t stime; /* tx slot time */ - u_int32_t preamble_len; /* size of tx preamble */ - u_int32_t preamble_pattern; /* pattern for tx preamble */ - u_int32_t tx_sframe_delim; /* tx delimiter */ - u_int32_t jsize; /* jam length */ - u_int32_t tx_pkt_max; /* tx max pkt size */ - u_int32_t tx_pkt_min; /* tx min pkt size */ - u_int32_t peak_attempt; /* count of tx peak attempts */ - u_int32_t dt_ctr; /* tx defer timer */ - u_int32_t nc_ctr; /* tx normal collision cntr */ - u_int32_t fc_ctr; /* tx first-collision cntr */ - u_int32_t ex_ctr; /* tx excess-collision cntr */ - u_int32_t lt_ctr; /* tx late-collision cntr */ - u_int32_t rand_seed; /* tx random number seed */ - u_int32_t tx_smachine; /* tx state machine */ - u_int32_t _unused3[44]; /* reserved */ - u_int32_t rx_swreset; /* rx software reset */ - u_int32_t rx_cfg; /* rx config register */ - u_int32_t rx_pkt_max; /* rx max pkt size */ - u_int32_t rx_pkt_min; /* rx min pkt size */ - u_int32_t mac_addr2; /* ethernet address 2 (MSB) */ - u_int32_t mac_addr1; /* ethernet address 1 */ - u_int32_t mac_addr0; /* ethernet address 0 (LSB) */ - u_int32_t fr_ctr; /* rx frame receive cntr */ - u_int32_t gle_ctr; /* rx giant-len error cntr */ - u_int32_t unale_ctr; /* rx unaligned error cntr */ - u_int32_t rcrce_ctr; /* rx CRC error cntr */ - u_int32_t rx_smachine; /* rx state machine */ - u_int32_t rx_cvalid; /* rx code violation */ - u_int32_t _unused4; /* reserved */ - u_int32_t htable3; /* hash table 3 */ - u_int32_t htable2; /* hash table 2 */ - u_int32_t htable1; /* hash table 1 */ - u_int32_t htable0; /* hash table 0 */ - u_int32_t afilter2; /* address filter 2 */ - u_int32_t afilter1; /* address filter 1 */ - u_int32_t afilter0; /* address filter 0 */ - u_int32_t afilter_mask; /* address filter mask */ + uint32_t xif_cfg; /* XIF config */ + uint32_t _unused[63]; /* reserved */ + uint32_t stat; /* status, clear on read */ + uint32_t imask; /* interrupt mask */ + uint32_t _unused2[64]; /* reserved */ + uint32_t tx_swreset; /* tx software reset */ + uint32_t tx_cfg; /* tx config */ + uint32_t ipkt_gap1; /* inter-packet gap 1 */ + uint32_t ipkt_gap2; /* inter-packet gap 2 */ + uint32_t attempt_limit; /* tx attempt limit */ + uint32_t stime; /* tx slot time */ + uint32_t preamble_len; /* size of tx preamble */ + uint32_t preamble_pattern; /* pattern for tx preamble */ + uint32_t tx_sframe_delim; /* tx delimiter */ + uint32_t jsize; /* jam length */ + uint32_t tx_pkt_max; /* tx max pkt size */ + uint32_t tx_pkt_min; /* tx min pkt size */ + uint32_t peak_attempt; /* count of tx peak attempts */ + uint32_t dt_ctr; /* tx defer timer */ + uint32_t nc_ctr; /* tx normal collision cntr */ + uint32_t fc_ctr; /* tx first-collision cntr */ + uint32_t ex_ctr; /* tx excess-collision cntr */ + uint32_t lt_ctr; /* tx late-collision cntr */ + uint32_t rand_seed; /* tx random number seed */ + uint32_t tx_smachine; /* tx state machine */ + uint32_t _unused3[44]; /* reserved */ + uint32_t rx_swreset; /* rx software reset */ + uint32_t rx_cfg; /* rx config register */ + uint32_t rx_pkt_max; /* rx max pkt size */ + uint32_t rx_pkt_min; /* rx min pkt size */ + uint32_t mac_addr2; /* ethernet address 2 (MSB) */ + uint32_t mac_addr1; /* ethernet address 1 */ + uint32_t mac_addr0; /* ethernet address 0 (LSB) */ + uint32_t fr_ctr; /* rx frame receive cntr */ + uint32_t gle_ctr; /* rx giant-len error cntr */ + uint32_t unale_ctr; /* rx unaligned error cntr */ + uint32_t rcrce_ctr; /* rx CRC error cntr */ + uint32_t rx_smachine; /* rx state machine */ + uint32_t rx_cvalid; /* rx code violation */ + uint32_t _unused4; /* reserved */ + uint32_t htable3; /* hash table 3 */ + uint32_t htable2; /* hash table 2 */ + uint32_t htable1; /* hash table 1 */ + uint32_t htable0; /* hash table 0 */ + uint32_t afilter2; /* address filter 2 */ + uint32_t afilter1; /* address filter 1 */ + uint32_t afilter0; /* address filter 0 */ + uint32_t afilter_mask; /* address filter mask */ }; #endif /* register indices: */ @@ -207,19 +207,19 @@ */ #if 0 struct be_cregs { - u_int32_t ctrl; /* control */ - u_int32_t stat; /* status */ - u_int32_t rxds; /* rx descriptor ring ptr */ - u_int32_t txds; /* tx descriptor ring ptr */ - u_int32_t rimask; /* rx interrupt mask */ - u_int32_t timask; /* tx interrupt mask */ - u_int32_t qmask; /* qec error interrupt mask */ - u_int32_t bmask; /* be error interrupt mask */ - u_int32_t rxwbufptr; /* local memory rx write ptr */ - u_int32_t rxrbufptr; /* local memory rx read ptr */ - u_int32_t txwbufptr; /* local memory tx write ptr */ - u_int32_t txrbufptr; /* local memory tx read ptr */ - u_int32_t ccnt; /* collision counter */ + uint32_t ctrl; /* control */ + uint32_t stat; /* status */ + uint32_t rxds; /* rx descriptor ring ptr */ + uint32_t txds; /* tx descriptor ring ptr */ + uint32_t rimask; /* rx interrupt mask */ + uint32_t timask; /* tx interrupt mask */ + uint32_t qmask; /* qec error interrupt mask */ + uint32_t bmask; /* be error interrupt mask */ + uint32_t rxwbufptr; /* local memory rx write ptr */ + uint32_t rxrbufptr; /* local memory rx read ptr */ + uint32_t txwbufptr; /* local memory tx write ptr */ + uint32_t txrbufptr; /* local memory tx read ptr */ + uint32_t ccnt; /* collision counter */ }; #endif /* register indices: */ @@ -270,8 +270,8 @@ */ #if 0 struct be_tregs { - u_int32_t tcvr_pal; /* transceiver pal */ - u_int32_t mgmt_pal; /* management pal */ + uint32_t tcvr_pal; /* transceiver pal */ + uint32_t mgmt_pal; /* management pal */ }; #endif /* register indices: */ Index: src/sys/dev/sbus/qe.c diff -u src/sys/dev/sbus/qe.c:1.54 src/sys/dev/sbus/qe.c:1.55 --- src/sys/dev/sbus/qe.c:1.54 Fri Sep 18 14:09:42 2009 +++ src/sys/dev/sbus/qe.c Sat Sep 19 11:53:42 2009 @@ -1,4 +1,4 @@ -/* $NetBSD: qe.c,v 1.54 2009/09/18 14:09:42 tsutsui Exp $ */ +/* $NetBSD: qe.c,v 1.55 2009/09/19 11:53:42 tsutsui Exp $ */ /*- * Copyright (c) 1999 The NetBSD Foundation, Inc. @@ -66,7 +66,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: qe.c,v 1.54 2009/09/18 14:09:42 tsutsui Exp $"); +__KERNEL_RCSID(0, "$NetBSD: qe.c,v 1.55 2009/09/19 11:53:42 tsutsui Exp $"); #define QEDEBUG @@ -141,7 +141,7 @@ struct qec_ring sc_rb; /* Packet Ring Buffer */ /* MAC address */ - u_int8_t sc_enaddr[6]; + uint8_t sc_enaddr[6]; #ifdef QEDEBUG int sc_debug; @@ -159,7 +159,7 @@ void qereset(struct qe_softc *); int qeintr(void *); -int qe_eint(struct qe_softc *, u_int32_t); +int qe_eint(struct qe_softc *, uint32_t); int qe_rint(struct qe_softc *); int qe_tint(struct qe_softc *); void qe_mcreset(struct qe_softc *); @@ -565,7 +565,7 @@ { struct qe_softc *sc = arg; bus_space_tag_t t = sc->sc_bustag; - u_int32_t qecstat, qestat; + uint32_t qecstat, qestat; int r = 0; #if defined(SUN4U) || defined(__GNUC__) @@ -718,7 +718,7 @@ * Error interrupt. */ int -qe_eint(struct qe_softc *sc, u_int32_t why) +qe_eint(struct qe_softc *sc, uint32_t why) { struct ifnet *ifp = &sc->sc_ethercom.ec_if; device_t self = &sc->sc_dev; @@ -982,8 +982,8 @@ bus_space_handle_t cr = sc->sc_cr; bus_space_handle_t mr = sc->sc_mr; struct qec_softc *qec = sc->sc_qec; - u_int32_t qecaddr; - u_int8_t *ea; + uint32_t qecaddr; + uint8_t *ea; int s; #if defined(SUN4U) || defined(__GNUC__) @@ -999,8 +999,8 @@ qec_meminit(&sc->sc_rb, QE_PKT_BUF_SZ); /* Channel registers: */ - bus_space_write_4(t, cr, QE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); - bus_space_write_4(t, cr, QE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); + bus_space_write_4(t, cr, QE_CRI_RXDS, (uint32_t)sc->sc_rb.rb_rxddma); + bus_space_write_4(t, cr, QE_CRI_TXDS, (uint32_t)sc->sc_rb.rb_txddma); bus_space_write_4(t, cr, QE_CRI_RIMASK, 0); bus_space_write_4(t, cr, QE_CRI_TIMASK, 0); @@ -1083,9 +1083,9 @@ bus_space_handle_t mr = sc->sc_mr; struct ether_multi *enm; struct ether_multistep step; - u_int32_t crc; - u_int16_t hash[4]; - u_int8_t octet, maccc, *ladrp = (u_int8_t *)&hash[0]; + uint32_t crc; + uint16_t hash[4]; + uint8_t octet, maccc, *ladrp = (uint8_t *)&hash[0]; int i, j; #if defined(SUN4U) || defined(__GNUC__) @@ -1171,7 +1171,7 @@ struct qe_softc *sc = ifp->if_softc; bus_space_tag_t t = sc->sc_bustag; bus_space_handle_t mr = sc->sc_mr; - u_int8_t v; + uint8_t v; #if defined(SUN4U) || defined(__GNUC__) (void)&t; @@ -1211,7 +1211,7 @@ bus_space_tag_t t = sc->sc_bustag; bus_space_handle_t mr = sc->sc_mr; int newmedia = ifm->ifm_media; - u_int8_t plscc, phycc; + uint8_t plscc, phycc; #if defined(SUN4U) || defined(__GNUC__) (void)&t; Index: src/sys/dev/sbus/qec.c diff -u src/sys/dev/sbus/qec.c:1.49 src/sys/dev/sbus/qec.c:1.50 --- src/sys/dev/sbus/qec.c:1.49 Sat Sep 19 04:48:18 2009 +++ src/sys/dev/sbus/qec.c Sat Sep 19 11:53:42 2009 @@ -1,4 +1,4 @@ -/* $NetBSD: qec.c,v 1.49 2009/09/19 04:48:18 tsutsui Exp $ */ +/* $NetBSD: qec.c,v 1.50 2009/09/19 11:53:42 tsutsui Exp $ */ /*- * Copyright (c) 1998 The NetBSD Foundation, Inc. @@ -30,7 +30,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: qec.c,v 1.49 2009/09/19 04:48:18 tsutsui Exp $"); +__KERNEL_RCSID(0, "$NetBSD: qec.c,v 1.50 2009/09/19 11:53:42 tsutsui Exp $"); #include <sys/param.h> #include <sys/systm.h> @@ -254,7 +254,7 @@ { bus_space_tag_t t = sc->sc_bustag; bus_space_handle_t qr = sc->sc_regs; - u_int32_t v, burst = 0, psize; + uint32_t v, burst = 0, psize; int i; /* First, reset the controller */ @@ -347,8 +347,8 @@ * Initialize transmit buffer descriptors */ for (i = 0; i < QEC_XD_RING_MAXSIZE; i++) { - qr->rb_txd[i].xd_addr = (u_int32_t) - (txbufdma + (i % ntbuf) * pktbufsz); + qr->rb_txd[i].xd_addr = + (uint32_t)(txbufdma + (i % ntbuf) * pktbufsz); qr->rb_txd[i].xd_flags = 0; } @@ -356,8 +356,8 @@ * Initialize receive buffer descriptors */ for (i = 0; i < QEC_XD_RING_MAXSIZE; i++) { - qr->rb_rxd[i].xd_addr = (u_int32_t) - (rxbufdma + (i % nrbuf) * pktbufsz); + qr->rb_rxd[i].xd_addr = + (uint32_t)(rxbufdma + (i % nrbuf) * pktbufsz); qr->rb_rxd[i].xd_flags = (i < nrbuf) ? QEC_XD_OWN | (pktbufsz & QEC_XD_LENGTH) : 0; Index: src/sys/dev/sbus/qecreg.h diff -u src/sys/dev/sbus/qecreg.h:1.3 src/sys/dev/sbus/qecreg.h:1.4 --- src/sys/dev/sbus/qecreg.h:1.3 Mon Apr 28 20:23:57 2008 +++ src/sys/dev/sbus/qecreg.h Sat Sep 19 11:53:42 2009 @@ -1,4 +1,4 @@ -/* $NetBSD: qecreg.h,v 1.3 2008/04/28 20:23:57 martin Exp $ */ +/* $NetBSD: qecreg.h,v 1.4 2009/09/19 11:53:42 tsutsui Exp $ */ /*- * Copyright (c) 1998 The NetBSD Foundation, Inc. @@ -58,16 +58,17 @@ /* * QEC registers layout - *- + */ +#if 0 struct qecregs { - u_int32_t qec_ctrl; // control - u_int32_t qec_stat; // status - u_int32_t qec_psize; // packet size - u_int32_t qec_msize; // local-mem size (64K) - u_int32_t qec_rsize; // receive partition size - u_int32_t qec_tsize; // transmit partition size + uint32_t qec_ctrl; /* control */ + uint32_t qec_stat; /* status */ + uint32_t qec_psize; /* packet size */ + uint32_t qec_msize; /* local-mem size (64K) */ + uint32_t qec_rsize; /* receive partition size */ + uint32_t qec_tsize; /* transmit partition size */ }; - */ +#endif #define QEC_QRI_CTRL (0*4) #define QEC_QRI_STAT (1*4) #define QEC_QRI_PSIZE (2*4) @@ -101,8 +102,8 @@ * Transmit & receive buffer descriptor. */ struct qec_xd { - volatile u_int32_t xd_flags; /* see below */ - volatile u_int32_t xd_addr; /* Buffer address (DMA) */ + volatile uint32_t xd_flags; /* see below */ + volatile uint32_t xd_addr; /* Buffer address (DMA) */ }; #define QEC_XD_OWN 0x80000000 /* ownership: 1=hw, 0=sw */ #define QEC_XD_SOP 0x40000000 /* start of packet marker (xmit) */ Index: src/sys/dev/sbus/qereg.h diff -u src/sys/dev/sbus/qereg.h:1.6 src/sys/dev/sbus/qereg.h:1.7 --- src/sys/dev/sbus/qereg.h:1.6 Mon Apr 28 20:23:57 2008 +++ src/sys/dev/sbus/qereg.h Sat Sep 19 11:53:42 2009 @@ -1,4 +1,4 @@ -/* $NetBSD: qereg.h,v 1.6 2008/04/28 20:23:57 martin Exp $ */ +/* $NetBSD: qereg.h,v 1.7 2009/09/19 11:53:42 tsutsui Exp $ */ /*- * Copyright (c) 1999 The NetBSD Foundation, Inc. @@ -61,20 +61,20 @@ */ #if 0 struct qe_cregs { - u_int32_t ctrl; /* control */ - u_int32_t stat; /* status */ - u_int32_t rxds; /* rx descriptor ring ptr */ - u_int32_t txds; /* tx descriptor ring ptr */ - u_int32_t rimask; /* rx interrupt mask */ - u_int32_t timask; /* tx interrupt mask */ - u_int32_t qmask; /* qec error interrupt mask */ - u_int32_t mmask; /* mace error interrupt mask */ - u_int32_t rxwbufptr; /* local memory rx write ptr */ - u_int32_t rxrbufptr; /* local memory rx read ptr */ - u_int32_t txwbufptr; /* local memory tx write ptr */ - u_int32_t txrbufptr; /* local memory tx read ptr */ - u_int32_t ccnt; /* collision counter */ - u_int32_t pipg; /* inter-frame gap */ + uint32_t ctrl; /* control */ + uint32_t stat; /* status */ + uint32_t rxds; /* rx descriptor ring ptr */ + uint32_t txds; /* tx descriptor ring ptr */ + uint32_t rimask; /* rx interrupt mask */ + uint32_t timask; /* tx interrupt mask */ + uint32_t qmask; /* qec error interrupt mask */ + uint32_t mmask; /* mace error interrupt mask */ + uint32_t rxwbufptr; /* local memory rx write ptr */ + uint32_t rxrbufptr; /* local memory rx read ptr */ + uint32_t txwbufptr; /* local memory tx write ptr */ + uint32_t txrbufptr; /* local memory tx read ptr */ + uint32_t ccnt; /* collision counter */ + uint32_t pipg; /* inter-frame gap */ }; #endif /* register indices: */ @@ -184,38 +184,38 @@ */ #if 0 struct qe_mregs { - u_int8_t rcvfifo; [0] /* receive fifo */ - u_int8_t xmtfifo; [1] /* transmit fifo */ - u_int8_t xmtfc; [2] /* transmit frame control */ - u_int8_t xmtfs; [3] /* transmit frame status */ - u_int8_t xmtrc; [4] /* tx retry count */ - u_int8_t rcvfc; [5] /* receive frame control */ - u_int8_t rcvfs; [6] /* receive frame status */ - u_int8_t fifofc; [7] /* fifo frame count */ - u_int8_t ir; [8] /* interrupt register */ - u_int8_t imr; [9] /* interrupt mask register */ - u_int8_t pr; [10] /* poll register */ - u_int8_t biucc; [11] /* biu config control */ - u_int8_t fifocc; [12] /* fifo config control */ - u_int8_t maccc; [13] /* mac config control */ - u_int8_t plscc; [14] /* pls config control */ - u_int8_t phycc; [15] /* phy config control */ - u_int8_t chipid1; [16] /* chipid, low byte */ - u_int8_t chipid2; [17] /* chipid, high byte */ - u_int8_t iac; [18] /* internal address config */ - u_int8_t _reserved0; [19] /* reserved */ - u_int8_t ladrf; [20] /* logical address filter */ - u_int8_t padr; [21] /* physical address */ - u_int8_t _reserved1; [22] /* reserved */ - u_int8_t _reserved2; [23] /* reserved */ - u_int8_t mpc; [24] /* missed packet count */ - u_int8_t _reserved3; [25] /* reserved */ - u_int8_t rntpc; [26] /* runt packet count */ - u_int8_t rcvcc; [27] /* receive collision count */ - u_int8_t _reserved4; [28] /* reserved */ - u_int8_t utr; [29] /* user test register */ - u_int8_t rtr1; [30] /* reserved test register 1 */ - u_int8_t rtr2; [31] /* reserved test register 2 */ + uint8_t rcvfifo; /* [0] receive fifo */ + uint8_t xmtfifo; /* [1] transmit fifo */ + uint8_t xmtfc; /* [2] transmit frame control */ + uint8_t xmtfs; /* [3] transmit frame status */ + uint8_t xmtrc; /* [4] tx retry count */ + uint8_t rcvfc; /* [5] receive frame control */ + uint8_t rcvfs; /* [6] receive frame status */ + uint8_t fifofc; /* [7] fifo frame count */ + uint8_t ir; /* [8] interrupt register */ + uint8_t imr; /* [9] interrupt mask register */ + uint8_t pr; /* [10] poll register */ + uint8_t biucc; /* [11] biu config control */ + uint8_t fifocc; /* [12] fifo config control */ + uint8_t maccc; /* [13] mac config control */ + uint8_t plscc; /* [14] pls config control */ + uint8_t phycc; /* [15] phy config control */ + uint8_t chipid1; /* [16] chipid, low byte */ + uint8_t chipid2; /* [17] chipid, high byte */ + uint8_t iac; /* [18] internal address config */ + uint8_t _reserved0; /* [19] reserved */ + uint8_t ladrf; /* [20] logical address filter */ + uint8_t padr; /* [21] physical address */ + uint8_t _reserved1; /* [22] reserved */ + uint8_t _reserved2; /* [23] reserved */ + uint8_t mpc; /* [24] missed packet count */ + uint8_t _reserved3; /* [25] reserved */ + uint8_t rntpc; /* [26] runt packet count */ + uint8_t rcvcc; /* [27] receive collision count */ + uint8_t _reserved4; /* [28] reserved */ + uint8_t utr; /* [29] user test register */ + uint8_t rtr1; /* [30] reserved test register 1 */ + uint8_t rtr2; /* [31] reserved test register 2 */ }; #endif /* register indices: */