Module Name: src
Committed By: cliff
Date: Mon Nov 9 10:00:02 UTC 2009
Modified Files:
src/sys/arch/mips/mips [matt-nb5-mips64]: db_interface.c
Log Message:
arch/mips/mips/db_interface.c
- add MIPS64_SHOW32() and MIPS64_SHOW64() macros
to show MIPS64 specific cp0 regs
- add EIRR, EIMR, EBASE, CONFIG[0,1,7] to show regs
>>> these switched by runtime vairable is_rmi_xls
is there a better variable to use ???
cpu_arch == 64 ??
- add mach mtcr, mfcr MD ddb commande
>>> these are not runtime switched based on cpu arch,
they are just 'there'
if you use them on the wrong CPU, it's your problem!
To generate a diff of this commit:
cvs rdiff -u -r1.64.16.6 -r1.64.16.7 src/sys/arch/mips/mips/db_interface.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/db_interface.c
diff -u src/sys/arch/mips/mips/db_interface.c:1.64.16.6 src/sys/arch/mips/mips/db_interface.c:1.64.16.7
--- src/sys/arch/mips/mips/db_interface.c:1.64.16.6 Tue Sep 15 05:12:53 2009
+++ src/sys/arch/mips/mips/db_interface.c Mon Nov 9 10:00:02 2009
@@ -1,4 +1,4 @@
-/* $NetBSD: db_interface.c,v 1.64.16.6 2009/09/15 05:12:53 matt Exp $ */
+/* $NetBSD: db_interface.c,v 1.64.16.7 2009/11/09 10:00:02 cliff Exp $ */
/*
* Mach Operating System
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.64.16.6 2009/09/15 05:12:53 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.64.16.7 2009/11/09 10:00:02 cliff Exp $");
#include "opt_cputype.h" /* which mips CPUs do we support? */
#include "opt_ddb.h"
@@ -58,6 +58,7 @@
#include <ddb/db_sym.h>
#include <ddb/db_extern.h>
#include <ddb/db_interface.h>
+#include <ddb/db_lex.h>
#endif
int db_active = 0;
@@ -67,6 +68,8 @@
void db_tlbdump_cmd(db_expr_t, bool, db_expr_t, const char *);
void db_kvtophys_cmd(db_expr_t, bool, db_expr_t, const char *);
void db_cp0dump_cmd(db_expr_t, bool, db_expr_t, const char *);
+void db_mfcr_cmd(db_expr_t, bool, db_expr_t, const char *);
+void db_mtcr_cmd(db_expr_t, bool, db_expr_t, const char *);
static void kdbpoke_4(vaddr_t addr, int newval);
static void kdbpoke_2(vaddr_t addr, short newval);
@@ -434,10 +437,60 @@
"", __val); \
} while (0)
+#define MIPS64_SHOW32(num, sel, name) \
+do { \
+ uint32_t __val; \
+ \
+ __asm volatile( \
+ ".set mips64 \n\t" \
+ "mfc0 %0,$" ___STRING(num) "," ___STRING(sel) "\n\t" \
+ : "=r"(__val)); \
+ printf(" %s:%*s %#x\n", name, FLDWIDTH - (int) strlen(name), \
+ "", __val); \
+} while (0)
+
+/* XXX not 64-bit ABI safe! */
+#define MIPS64_SHOW64(num, sel, name) \
+do { \
+ uint64_t __val; \
+ \
+ __asm volatile( \
+ ".set push \n\t" \
+ ".set mips64 \n\t" \
+ ".set noat \n\t" \
+ "dmfc0 $1,$" ___STRING(num) "," ___STRING(sel) "\n\t" \
+ "dsll %L0,$1,32 \n\t" \
+ "dsrl %L0,%L0,32 \n\t" \
+ "dsrl %M0,$1,32 \n\t" \
+ ".set pop" \
+ : "=r"(__val)); \
+ printf(" %s:%*s %#"PRIx64"x\n", name, FLDWIDTH - (int) strlen(name), \
+ "", __val); \
+} while (0)
+
void
db_cp0dump_cmd(db_expr_t addr, bool have_addr, db_expr_t count,
const char *modif)
{
+ int is_rmi_xls=0;
+
+ /* XXX FIXME what class define to use here ? */
+ switch (MIPS_PRID_IMPL(cpu_id)) {
+ case MIPS_XLS104:
+ case MIPS_XLS108:
+ case MIPS_XLS204:
+ case MIPS_XLS208:
+ case MIPS_XLS404LITE:
+ case MIPS_XLS408LITE:
+ case MIPS_XLS404:
+ case MIPS_XLS408:
+ case MIPS_XLS416:
+ case MIPS_XLS608:
+ case MIPS_XLS616:
+ is_rmi_xls = 1;
+ break;
+ }
+
SHOW32(MIPS_COP_0_TLB_INDEX, "index");
SHOW32(MIPS_COP_0_TLB_RANDOM, "random");
@@ -475,6 +528,12 @@
SHOW32(MIPS_COP_0_COUNT, "count");
}
+ /* XXX FIXME what class define to use here ? */
+ if (is_rmi_xls) {
+ MIPS64_SHOW64(9, 6, "eirr");
+ MIPS64_SHOW64(9, 7, "eimr");
+ }
+
if (CPUIS64BITS) {
SHOW64(MIPS_COP_0_TLB_HI, "entryhi");
} else {
@@ -495,16 +554,24 @@
}
SHOW32(MIPS_COP_0_PRID, "prid");
- SHOW32(MIPS_COP_0_CONFIG, "config");
+ /* XXX FIXME what class define to use here ? */
+ if (is_rmi_xls) {
+ MIPS64_SHOW32(15, 1, "ebase");
+ MIPS64_SHOW32(16, 0, "config0");
+ MIPS64_SHOW32(16, 1, "config1");
+ MIPS64_SHOW32(16, 7, "config7");
+ } else {
+ SHOW32(MIPS_COP_0_CONFIG, "config");
#if defined(MIPS32) || defined(MIPS64)
- if (CPUISMIPSNN) {
- uint32_t val;
+ if (CPUISMIPSNN) {
+ uint32_t val;
- val = mipsNN_cp0_config1_read();
- printf(" config1: %#x\n", val);
- }
+ val = mipsNN_cp0_config1_read();
+ printf(" config1: %#x\n", val);
+ }
#endif
+ }
if (MIPS_HAS_LLSC) {
if (MIPS_HAS_LLADDR) {
@@ -531,10 +598,12 @@
}
}
-#if !defined(MIPS64_XLS) /* CP0 ECC and CACHE_ERR "not implemented" */
- SHOW32(MIPS_COP_0_ECC, "ecc");
- SHOW32(MIPS_COP_0_CACHE_ERR, "cacherr");
-#endif
+ /* CP0 ECC and CACHE_ERR "not implemented" on XLS */
+ if (!is_rmi_xls) {
+ SHOW32(MIPS_COP_0_ECC, "ecc");
+ SHOW32(MIPS_COP_0_CACHE_ERR, "cacherr");
+ }
+
SHOW32(MIPS_COP_0_TAG_LO, "cachelo");
SHOW32(MIPS_COP_0_TAG_HI, "cachehi");
@@ -546,6 +615,37 @@
}
}
+void
+db_mfcr_cmd(db_expr_t addr, bool have_addr, db_expr_t count,
+ const char *modif)
+{
+ extern uint64_t rmixls_mfcr(u_int);
+
+ if (!have_addr)
+ return;
+ db_printf("control reg 0x%lx = 0x%" PRIx64 "\n", addr,
+ rmixls_mfcr(addr));
+}
+
+void
+db_mtcr_cmd(db_expr_t addr, bool have_addr, db_expr_t count,
+ const char *modif)
+{
+ db_expr_t value;
+ extern void rmixls_mtcr(uint64_t, u_int);
+
+ if (!have_addr)
+ return;
+ if (db_expression(&value) == 0) {
+ db_printf("Address missing\n");
+ db_flush_lex();
+ return;
+ }
+ db_skip_to_eol();
+ rmixls_mtcr(value, addr);
+ db_printf("control reg 0x%lx = 0x%" PRIx64 "\n", addr, value);
+}
+
const struct db_command db_machine_command_table[] = {
{ DDB_ADD_CMD("cp0", db_cp0dump_cmd, 0,
"Dump CP0 registers.",
@@ -557,6 +657,12 @@
{ DDB_ADD_CMD("tlb", db_tlbdump_cmd, 0,
"Print out TLB entries. (only works with options DEBUG)",
NULL, NULL) },
+ { DDB_ADD_CMD("mfcr", db_mfcr_cmd, CS_NOREPEAT,
+ "Dump processor control register",
+ NULL, NULL) },
+ { DDB_ADD_CMD("mtcr", db_mtcr_cmd, CS_NOREPEAT|CS_MORE,
+ "Dump processor control register",
+ NULL, NULL) },
{ DDB_ADD_CMD(NULL, NULL, 0, NULL,NULL,NULL) }
};
#endif /* !KGDB */
