Module Name: src
Committed By: cliff
Date: Fri Nov 13 05:25:50 UTC 2009
Modified Files:
src/sys/arch/mips/mips [matt-nb5-mips64]: mips_machdep.c
Log Message:
- pridtab definition is removed to cpu.h
- pritab entries now initialize cpu_cp0flags and cpu_cidflags
except for RMI XLS entries, these are all 0 for now.
- pridtab entries for RMI XLS use those new fields and CPU_MIPS_HAVE_MxCR
To generate a diff of this commit:
cvs rdiff -u -r1.205.4.1.2.1.2.16 -r1.205.4.1.2.1.2.17 \
src/sys/arch/mips/mips/mips_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/mips_machdep.c
diff -u src/sys/arch/mips/mips/mips_machdep.c:1.205.4.1.2.1.2.16 src/sys/arch/mips/mips/mips_machdep.c:1.205.4.1.2.1.2.17
--- src/sys/arch/mips/mips/mips_machdep.c:1.205.4.1.2.1.2.16 Tue Nov 3 16:30:58 2009
+++ src/sys/arch/mips/mips/mips_machdep.c Fri Nov 13 05:25:49 2009
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.16 2009/11/03 16:30:58 uebayasi Exp $ */
+/* $NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.17 2009/11/13 05:25:49 cliff Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -112,7 +112,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.16 2009/11/03 16:30:58 uebayasi Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.17 2009/11/13 05:25:49 cliff Exp $");
#include "opt_cputype.h"
#include "opt_compat_netbsd32.h"
@@ -153,6 +153,7 @@
#include <mips/frame.h>
#include <mips/regnum.h>
+#include <mips/cpu.h>
#include <mips/locore.h>
#include <mips/psl.h>
#include <mips/pte.h>
@@ -235,16 +236,6 @@
char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */
char cpu_model[128];
-struct pridtab {
- int cpu_cid;
- int cpu_pid;
- int cpu_rev; /* -1 == wildcard */
- int cpu_copts; /* -1 == wildcard */
- int cpu_isa; /* -1 == probed (mips32/mips64) */
- int cpu_ntlb; /* -1 == unknown, 0 == probed */
- int cpu_flags;
- const char *cpu_name;
-};
/*
* Assumptions:
@@ -260,19 +251,19 @@
#define MIPS32_FLAGS CPU_MIPS_R4K_MMU | CPU_MIPS_CAUSE_IV | CPU_MIPS_USE_WAIT
#define MIPS64_FLAGS MIPS32_FLAGS /* same as MIPS32 flags (for now) */
-static const struct pridtab *mycpu;
+const struct pridtab *mycpu;
static const struct pridtab cputab[] = {
{ 0, MIPS_R2000, -1, -1, CPU_ARCH_MIPS1, 64,
- CPU_MIPS_NO_LLSC, "MIPS R2000 CPU" },
+ CPU_MIPS_NO_LLSC, 0, 0, "MIPS R2000 CPU" },
{ 0, MIPS_R3000, MIPS_REV_R2000A, -1, CPU_ARCH_MIPS1, 64,
- CPU_MIPS_NO_LLSC, "MIPS R2000A CPU" },
+ CPU_MIPS_NO_LLSC, 0, 0, "MIPS R2000A CPU" },
{ 0, MIPS_R3000, MIPS_REV_R3000, -1, CPU_ARCH_MIPS1, 64,
- CPU_MIPS_NO_LLSC, "MIPS R3000 CPU" },
+ CPU_MIPS_NO_LLSC, 0, 0, "MIPS R3000 CPU" },
{ 0, MIPS_R3000, MIPS_REV_R3000A, -1, CPU_ARCH_MIPS1, 64,
- CPU_MIPS_NO_LLSC, "MIPS R3000A CPU" },
+ CPU_MIPS_NO_LLSC, 0, 0, "MIPS R3000A CPU" },
{ 0, MIPS_R6000, -1, -1, CPU_ARCH_MIPS2, 32,
- MIPS_NOT_SUPP, "MIPS R6000 CPU" },
+ MIPS_NOT_SUPP, 0, 0, "MIPS R6000 CPU" },
/*
* rev 0x00, 0x22 and 0x30 are R4000, 0x40, 0x50 and 0x60 are R4400.
@@ -280,52 +271,55 @@
* 0x40 - 0xff for R4400?
*/
{ 0, MIPS_R4000, MIPS_REV_R4000_A, -1, CPU_ARCH_MIPS3, 48,
- CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT,
+ CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0,
"MIPS R4000 CPU" },
{ 0, MIPS_R4000, MIPS_REV_R4000_B, -1, CPU_ARCH_MIPS3, 48,
- CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT,
+ CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0,
"MIPS R4000 CPU" },
{ 0, MIPS_R4000, MIPS_REV_R4000_C, -1, CPU_ARCH_MIPS3, 48,
- CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT,
+ CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0,
"MIPS R4000 CPU" },
{ 0, MIPS_R4000, MIPS_REV_R4400_A, -1, CPU_ARCH_MIPS3, 48,
- CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT,
+ CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0,
"MIPS R4400 CPU" },
{ 0, MIPS_R4000, MIPS_REV_R4400_B, -1, CPU_ARCH_MIPS3, 48,
- CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT,
+ CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0,
"MIPS R4400 CPU" },
{ 0, MIPS_R4000, MIPS_REV_R4400_C, -1, CPU_ARCH_MIPS3, 48,
- CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT,
+ CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0,
"MIPS R4400 CPU" },
{ 0, MIPS_R3LSI, -1, -1, CPU_ARCH_MIPS1, -1,
- MIPS_NOT_SUPP, "LSI Logic R3000 derivative" },
+ MIPS_NOT_SUPP, 0, 0, "LSI Logic R3000 derivative" },
{ 0, MIPS_R6000A, -1, -1, CPU_ARCH_MIPS2, 32,
- MIPS_NOT_SUPP, "MIPS R6000A CPU" },
+ MIPS_NOT_SUPP, 0, 0, "MIPS R6000A CPU" },
{ 0, MIPS_R3IDT, -1, -1, CPU_ARCH_MIPS1, -1,
- MIPS_NOT_SUPP, "IDT R3041 or RC36100 CPU" },
+ MIPS_NOT_SUPP, 0, 0, "IDT R3041 or RC36100 CPU" },
{ 0, MIPS_R4100, -1, -1, CPU_ARCH_MIPS3, 32,
- CPU_MIPS_R4K_MMU | CPU_MIPS_NO_LLSC, "NEC VR4100 CPU" },
+ CPU_MIPS_R4K_MMU | CPU_MIPS_NO_LLSC, 0, 0,
+ "NEC VR4100 CPU" },
{ 0, MIPS_R4200, -1, -1, CPU_ARCH_MIPS3, -1,
- MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, "NEC VR4200 CPU" },
+ MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, 0, 0,
+ "NEC VR4200 CPU" },
{ 0, MIPS_R4300, -1, -1, CPU_ARCH_MIPS3, 32,
- CPU_MIPS_R4K_MMU, "NEC VR4300 CPU" },
+ CPU_MIPS_R4K_MMU, 0, 0, "NEC VR4300 CPU" },
{ 0, MIPS_R4600, -1, -1, CPU_ARCH_MIPS3, 48,
- CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT,
+ CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0,
"QED R4600 Orion CPU" },
{ 0, MIPS_R4700, -1, -1, CPU_ARCH_MIPS3, 48,
- CPU_MIPS_R4K_MMU, "QED R4700 Orion CPU" },
+ CPU_MIPS_R4K_MMU, 0, 0, "QED R4700 Orion CPU" },
{ 0, MIPS_R8000, -1, -1, CPU_ARCH_MIPS4, 384,
- MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, "MIPS R8000 Blackbird/TFP CPU" },
+ MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, 0, 0,
+ "MIPS R8000 Blackbird/TFP CPU" },
{ 0, MIPS_R10000, -1, -1, CPU_ARCH_MIPS4, 64,
- CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT,
+ CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0,
"MIPS R10000 CPU" },
{ 0, MIPS_R12000, -1, -1, CPU_ARCH_MIPS4, 64,
- CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT,
+ CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0,
"MIPS R12000 CPU" },
{ 0, MIPS_R14000, -1, -1, CPU_ARCH_MIPS4, 64,
- CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT,
+ CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0,
"MIPS R14000 CPU" },
/* XXX
@@ -336,19 +330,19 @@
* the 4650...
*/
{ 0, MIPS_R4650, 0, -1, CPU_ARCH_MIPS3, -1,
- MIPS_NOT_SUPP /* no MMU! */, "QED R4650 CPU" },
+ MIPS_NOT_SUPP /* no MMU! */, 0, 0, "QED R4650 CPU" },
{ 0, MIPS_TX3900, MIPS_REV_TX3912, -1, CPU_ARCH_MIPS1, 32,
- CPU_MIPS_NO_LLSC, "Toshiba TX3912 CPU" },
+ CPU_MIPS_NO_LLSC, 0, 0, "Toshiba TX3912 CPU" },
{ 0, MIPS_TX3900, MIPS_REV_TX3922, -1, CPU_ARCH_MIPS1, 64,
- CPU_MIPS_NO_LLSC, "Toshiba TX3922 CPU" },
+ CPU_MIPS_NO_LLSC, 0, 0, "Toshiba TX3922 CPU" },
{ 0, MIPS_TX3900, MIPS_REV_TX3927, -1, CPU_ARCH_MIPS1, 64,
- CPU_MIPS_NO_LLSC, "Toshiba TX3927 CPU" },
+ CPU_MIPS_NO_LLSC, 0, 0, "Toshiba TX3927 CPU" },
{ 0, MIPS_R5000, -1, -1, CPU_ARCH_MIPS4, 48,
- CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT,
+ CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0,
"MIPS R5000 CPU" },
{ 0, MIPS_RM5200, -1, -1, CPU_ARCH_MIPS4, 48,
CPU_MIPS_R4K_MMU | CPU_MIPS_CAUSE_IV | CPU_MIPS_DOUBLE_COUNT |
- CPU_MIPS_USE_WAIT, "QED RM5200 CPU" },
+ CPU_MIPS_USE_WAIT, 0, 0, "QED RM5200 CPU" },
/* XXX
* The rm7000 rev 2.0 can have 64 tlbs, and has 6 extra interrupts. See
@@ -357,7 +351,7 @@
*/
{ 0, MIPS_RM7000, -1, -1, CPU_ARCH_MIPS4, 48,
MIPS_NOT_SUPP | CPU_MIPS_CAUSE_IV | CPU_MIPS_DOUBLE_COUNT |
- CPU_MIPS_USE_WAIT, "QED RM7000 CPU" },
+ CPU_MIPS_USE_WAIT, 0, 0, "QED RM7000 CPU" },
/*
* IDT RC32300 core is a 32 bit MIPS2 processor with
@@ -370,110 +364,127 @@
*
*/
{ 0, MIPS_RC32300, -1, -1, CPU_ARCH_MIPS3, 16,
- MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, "IDT RC32300 CPU" },
+ MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, 0, 0,
+ "IDT RC32300 CPU" },
{ 0, MIPS_RC32364, -1, -1, CPU_ARCH_MIPS3, 16,
- MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, "IDT RC32364 CPU" },
+ MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, 0, 0,
+ "IDT RC32364 CPU" },
{ 0, MIPS_RC64470, -1, -1, CPU_ARCH_MIPSx, -1,
- MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, "IDT RC64474/RC64475 CPU" },
+ MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, 0, 0,
+ "IDT RC64474/RC64475 CPU" },
{ 0, MIPS_R5400, -1, -1, CPU_ARCH_MIPSx, -1,
- MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, "NEC VR5400 CPU" },
+ MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, 0, 0,
+ "NEC VR5400 CPU" },
{ 0, MIPS_R5900, -1, -1, CPU_ARCH_MIPS3, 48,
- CPU_MIPS_NO_LLSC | CPU_MIPS_R4K_MMU, "Toshiba R5900 CPU" },
+ CPU_MIPS_NO_LLSC | CPU_MIPS_R4K_MMU, 0, 0,
+ "Toshiba R5900 CPU" },
{ 0, MIPS_TX4900, MIPS_REV_TX4927, -1, CPU_ARCH_MIPS3, 48,
- CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT,
+ CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0,
"Toshiba TX4927 CPU" },
{ 0, MIPS_TX4900, -1, -1, CPU_ARCH_MIPS3, 48,
- CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT,
+ CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0,
"Toshiba TX4900 CPU" },
#if 0 /* ID collisions : can we use a CU1 test or similar? */
{ 0, MIPS_R3SONY, -1, -1, CPU_ARCH_MIPS1, -1,
- MIPS_NOT_SUPP, "SONY R3000 derivative" }, /* 0x21; crash R4700? */
+ MIPS_NOT_SUPP, 0, 0, "SONY R3000 derivative" }, /* 0x21; crash R4700? */
{ 0, MIPS_R3NKK, -1, -1, CPU_ARCH_MIPS1, -1,
- MIPS_NOT_SUPP, "NKK R3000 derivative" }, /* 0x23; crash R5000? */
+ MIPS_NOT_SUPP, 0, 0, "NKK R3000 derivative" }, /* 0x23; crash R5000? */
#endif
{ MIPS_PRID_CID_MTI, MIPS_4Kc, -1, -1, -1, 0,
- MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, "4Kc" },
+ MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "4Kc" },
{ MIPS_PRID_CID_MTI, MIPS_4KEc, -1, -1, -1, 0,
- MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, "4KEc" },
+ MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "4KEc" },
{ MIPS_PRID_CID_MTI, MIPS_4KEc_R2, -1, -1, -1, 0,
- MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, "4KEc (Rev 2)" },
+ MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "4KEc (Rev 2)" },
{ MIPS_PRID_CID_MTI, MIPS_4KSc, -1, -1, -1, 0,
- MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, "4KSc" },
+ MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "4KSc" },
{ MIPS_PRID_CID_MTI, MIPS_5Kc, -1, -1, -1, 0,
- MIPS64_FLAGS | CPU_MIPS_DOUBLE_COUNT, "5Kc" },
+ MIPS64_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "5Kc" },
{ MIPS_PRID_CID_MTI, MIPS_20Kc, -1, -1, -1, 0,
- MIPS64_FLAGS, "20Kc" },
+ MIPS64_FLAGS, 0, 0, "20Kc" },
{ MIPS_PRID_CID_MTI, MIPS_24K, -1, -1, -1, 0,
- MIPS64_FLAGS | CPU_MIPS_DOUBLE_COUNT, "24K" },
+ MIPS64_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "24K" },
{ MIPS_PRID_CID_MTI, MIPS_24KE, -1, -1, -1, 0,
- MIPS64_FLAGS | CPU_MIPS_DOUBLE_COUNT, "24KE" },
+ MIPS64_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "24KE" },
{ MIPS_PRID_CID_MTI, MIPS_34K, -1, -1, -1, 0,
- MIPS64_FLAGS | CPU_MIPS_DOUBLE_COUNT, "34K" },
+ MIPS64_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "34K" },
{ MIPS_PRID_CID_MTI, MIPS_74K, -1, -1, -1, 0,
- MIPS64_FLAGS | CPU_MIPS_DOUBLE_COUNT, "74K" },
+ MIPS64_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "74K" },
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1000, -1, 0,
- MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT,
+ MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, 0, 0,
"Au1000 (Rev 1 core)" },
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1000, -1, 0,
- MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT,
+ MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, 0, 0,
"Au1000 (Rev 2 core)" },
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1100, -1, 0,
- MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT,
+ MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, 0, 0,
"Au1100 (Rev 1 core)" },
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1100, -1, 0,
- MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT,
+ MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, 0, 0,
"Au1100 (Rev 2 core)" },
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1500, -1, 0,
- MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT,
+ MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, 0, 0,
"Au1500 (Rev 1 core)" },
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1500, -1, 0,
- MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT,
+ MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, 0, 0,
"Au1500 (Rev 2 core)" },
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1550, -1, 0,
- MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT,
+ MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, 0, 0,
"Au1550 (Rev 2 core)" },
/* The SB-1 CPU uses a CCA of 5 - "Cacheable Coherent Shareable" */
{ MIPS_PRID_CID_SIBYTE, MIPS_SB1, -1, -1, -1, 0,
MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT |
- CPU_MIPS_HAVE_SPECIAL_CCA | (5 << CPU_MIPS_CACHED_CCA_SHIFT),
+ CPU_MIPS_HAVE_SPECIAL_CCA | (5 << CPU_MIPS_CACHED_CCA_SHIFT), 0, 0,
"SB-1" },
{ MIPS_PRID_CID_RMI, MIPS_XLS616, -1, -1, -1, 0,
- MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR,
- "XLS616" },
+ MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR |
+ CPU_MIPS_HAVE_MxCR,
+ MIPS_CP0FL_USE |MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
+ MIPS_CP0FL_CONFIGn(0) | MIPS_CP0FL_CONFIGn(1) | MIPS_CP0FL_CONFIGn(7),
+ CIDFL_RMI_TYPE_XLS, "XLS616" },
{ MIPS_PRID_CID_RMI, MIPS_XLS416, -1, -1, -1, 0,
- MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR,
- "XLS416" },
+ MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR |
+ CPU_MIPS_HAVE_MxCR,
+ MIPS_CP0FL_USE |MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
+ MIPS_CP0FL_CONFIGn(0) | MIPS_CP0FL_CONFIGn(1) | MIPS_CP0FL_CONFIGn(7),
+ CIDFL_RMI_TYPE_XLS, "XLS416" },
{ MIPS_PRID_CID_RMI, MIPS_XLS408, -1, -1, -1, 0,
- MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR,
- "XLS408" },
+ MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR |
+ CPU_MIPS_HAVE_MxCR,
+ MIPS_CP0FL_USE |MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
+ MIPS_CP0FL_CONFIGn(0) | MIPS_CP0FL_CONFIGn(1) | MIPS_CP0FL_CONFIGn(7),
+ CIDFL_RMI_TYPE_XLS, "XLS408" },
{ MIPS_PRID_CID_RMI, MIPS_XLS408LITE, -1, -1, -1, 0,
- MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR,
- "XLS408LITE" },
+ MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR |
+ CPU_MIPS_HAVE_MxCR,
+ MIPS_CP0FL_USE |MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
+ MIPS_CP0FL_CONFIGn(0) | MIPS_CP0FL_CONFIGn(1) | MIPS_CP0FL_CONFIGn(7),
+ CIDFL_RMI_TYPE_XLS, "XLS408LITE" },
{ 0, 0, 0, 0, 0, 0,
- 0, NULL }
+ 0, 0, 0, NULL }
};
static const struct pridtab fputab[] = {
- { 0, MIPS_SOFT, -1, 0, 0, 0, 0, "software emulated floating point" },
- { 0, MIPS_R2360, -1, 0, 0, 0, 0, "MIPS R2360 Floating Point Board" },
- { 0, MIPS_R2010, -1, 0, 0, 0, 0, "MIPS R2010 FPC" },
- { 0, MIPS_R3010, -1, 0, 0, 0, 0, "MIPS R3010 FPC" },
- { 0, MIPS_R6010, -1, 0, 0, 0, 0, "MIPS R6010 FPC" },
- { 0, MIPS_R4010, -1, 0, 0, 0, 0, "MIPS R4010 FPC" },
+ { 0, MIPS_SOFT, -1, 0, 0, 0, 0, 0, 0, "software emulated floating point" },
+ { 0, MIPS_R2360, -1, 0, 0, 0, 0, 0, 0, "MIPS R2360 Floating Point Board" },
+ { 0, MIPS_R2010, -1, 0, 0, 0, 0, 0, 0, "MIPS R2010 FPC" },
+ { 0, MIPS_R3010, -1, 0, 0, 0, 0, 0, 0, "MIPS R3010 FPC" },
+ { 0, MIPS_R6010, -1, 0, 0, 0, 0, 0, 0, "MIPS R6010 FPC" },
+ { 0, MIPS_R4010, -1, 0, 0, 0, 0, 0, 0, "MIPS R4010 FPC" },
};
/*
