Module Name: src
Committed By: cliff
Date: Mon Nov 9 10:07:44 UTC 2009
Modified Files:
src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixlreg.h
Log Message:
- RMIXL_IOREG_READ, RMIXL_IOREG_WRITE provide general use ops for
accessing on-chip DEV_IO regs w/ Big Endian byte order.
- add System Bridge Controller registers defines
- add Address Error registers defines
- add DRAM register defines
- add GPIO signal and system control register offsets
- add PCIE Interface controller register offsets
- fix typo for RMIXL_PIC_INTRACK
- add RMIXL_PIC_IRTENTRYC0_RESV
To generate a diff of this commit:
cvs rdiff -u -r1.1.2.3 -r1.1.2.4 src/sys/arch/mips/rmi/rmixlreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/rmi/rmixlreg.h
diff -u src/sys/arch/mips/rmi/rmixlreg.h:1.1.2.3 src/sys/arch/mips/rmi/rmixlreg.h:1.1.2.4
--- src/sys/arch/mips/rmi/rmixlreg.h:1.1.2.3 Fri Sep 25 22:20:43 2009
+++ src/sys/arch/mips/rmi/rmixlreg.h Mon Nov 9 10:07:44 2009
@@ -1,4 +1,4 @@
-/* $NetBSD: rmixlreg.h,v 1.1.2.3 2009/09/25 22:20:43 cliff Exp $ */
+/* $NetBSD: rmixlreg.h,v 1.1.2.4 2009/11/09 10:07:44 cliff Exp $ */
/*-
* Copyright (c) 2009 The NetBSD Foundation, Inc.
@@ -33,6 +33,19 @@
#ifndef _MIPS_RMI_RMIXLREGS_H_
#define _MIPS_RMI_RMIXLREGS_H_
+#include <sys/endian.h>
+
+/*
+ * on chip I/O register byte order is
+ * BIG ENDIAN regardless of code model
+ */
+#define RMIXL_IOREG_VADDR(o) \
+ (volatile uint32_t *)MIPS_PHYS_TO_KSEG1( \
+ rmixl_configuration.rc_io_pbase + (o))
+#define RMIXL_IOREG_READ(o) be32toh(*RMIXL_IOREG_VADDR(o))
+#define RMIXL_IOREG_WRITE(o,v) *RMIXL_IOREG_VADDR(o) = htobe32(v)
+
+
/*
* RMIXL Coprocessor 2 registers:
*/
@@ -105,6 +118,8 @@
/* default virtual base address */
#define RMIXL_IO_DEV_SIZE 0x100000 /* I/O Conf. space is 1MB region */
+
+
/*
* Peripheral and I/O Configuration Region of Memory
*
@@ -115,7 +130,7 @@
*
* Device region offsets are relative to RMIXL_IO_DEV_PBASE.
*/
-#define RMIXL_IO_DEV_BRIDGE 0x00000 /* System Bridge Controller */
+#define RMIXL_IO_DEV_BRIDGE 0x00000 /* System Bridge Controller (SBC) */
#define RMIXL_IO_DEV_DDR_CHNA 0x01000 /* DDR1/DDR2 DRAM_A Channel, Port MA */
#define RMIXL_IO_DEV_DDR_CHNB 0x02000 /* DDR1/DDR2 DRAM_B Channel, Port MB */
#define RMIXL_IO_DEV_DDR_CHNC 0x03000 /* DDR1/DDR2 DRAM_C Channel, Port MC */
@@ -170,15 +185,157 @@
/*
- * Programmable Interrupt Controller registers
- * the Programming Reference Manual table 10.4
+ * the Programming Reference Manual
* lists "Reg ID" values not offsets;
- * assume offset = id * 4
+ * offset = id * 4
*/
#define _RMIXL_OFFSET(id) ((id) * 4)
+
+
+/*
+ * System Bridge Controller registers
+ * offsets are relative to RMIXL_IO_DEV_BRIDGE
+ */
+#define RMIXL_SBC_DRAM_NBARS 8
+#define RMIXL_SBC_DRAM_BAR(n) _RMIXL_OFFSET(0x000 + (n))
+ /* DRAM Region Base Address Regs[0-7] */
+#define RMIXL_SBC_DRAM_CHNAC_DTR(n) _RMIXL_OFFSET(0x008 + (n))
+ /* DRAM Region Channels A,C Address Translation Regs[0-7] */
+#define RMIXL_SBC_DRAM_CHNBD_DTR(n) _RMIXL_OFFSET(0x010 + (n))
+ /* DRAM Region Channels B,D Address Translation Regs[0-7] */
+#define RMIXL_SBC_DRAM_BRIDGE_CFG _RMIXL_OFFSET(0x18) /* SBC DRAM config reg */
+#define RMIXL_SBC_XLS_IO_BAR _RMIXL_OFFSET(0x19) /* I/O Config Base Addr reg */
+#define RMIXL_SBC_XLS_FLASH_BAR _RMIXL_OFFSET(0x20) /* Flash Memory Base Addr reg */
+#define RMIXL_SBC_PCIE_CFG_BAR _RMIXL_OFFSET(0x40) /* PCI Configuration BAR */
+#define RMIXL_SBC_PCIE_ECFG_BAR _RMIXL_OFFSET(0x41) /* PCI Extended Configuration BAR */
+#define RMIXL_SBC_PCIE_MEM_BAR _RMIXL_OFFSET(0x42) /* PCI Memory region BAR */
+#define RMIXL_SBC_PCIE_IO_BAR _RMIXL_OFFSET(0x43) /* PCI IO region BAR */
+
+/*
+ * Address Error registers
+ * offsets are relative to RMIXL_IO_DEV_BRIDGE
+ */
+#define RMIXL_ADDR_ERR_DEVICE_MASK _RMIXL_OFFSET(0x25) /* Address Error Device Mask */
+#define RMIXL_ADDR_ERR_AERR0_LOG1 _RMIXL_OFFSET(0x26) /* Address Error Set 0 Log 1 */
+#define RMIXL_ADDR_ERR_AERR0_LOG2 _RMIXL_OFFSET(0x27) /* Address Error Set 0 Log 2 */
+#define RMIXL_ADDR_ERR_AERR0_LOG3 _RMIXL_OFFSET(0x28) /* Address Error Set 0 Log 3 */
+#define RMIXL_ADDR_ERR_AERR0_DEVSTAT _RMIXL_OFFSET(0x29) /* Address Error Set 0 irpt status */
+#define RMIXL_ADDR_ERR_AERR1_LOG1 _RMIXL_OFFSET(0x2a) /* Address Error Set 1 Log 1 */
+#define RMIXL_ADDR_ERR_AERR1_LOG2 _RMIXL_OFFSET(0x2b) /* Address Error Set 1 Log 2 */
+#define RMIXL_ADDR_ERR_AERR1_LOG3 _RMIXL_OFFSET(0x2c) /* Address Error Set 1 Log 3 */
+#define RMIXL_ADDR_ERR_AERR1_DEVSTAT _RMIXL_OFFSET(0x2d) /* Address Error Set 1 irpt status */
+#define RMIXL_ADDR_ERR_AERR0_EN _RMIXL_OFFSET(0x2e) /* Address Error Set 0 irpt enable */
+#define RMIXL_ADDR_ERR_AERR0_UPG _RMIXL_OFFSET(0x2f) /* Address Error Set 0 Upgrade */
+#define RMIXL_ADDR_ERR_AERR0_CLEAR _RMIXL_OFFSET(0x30) /* Address Error Set 0 irpt clear */
+#define RMIXL_ADDR_ERR_AERR1_CLEAR _RMIXL_OFFSET(0x31) /* Address Error Set 1 irpt clear */
+#define RMIXL_ADDR_ERR_SBE_COUNTS _RMIXL_OFFSET(0x32) /* Single Bit Error Counts */
+#define RMIXL_ADDR_ERR_DBE_COUNTS _RMIXL_OFFSET(0x33) /* Double Bit Error Counts */
+#define RMIXL_ADDR_ERR_BITERR_INT_EN _RMIXL_OFFSET(0x33) /* Bit Error intr enable */
+
+/*
+ * RMIXL_SBC_DRAM_BAR bit defines
+ */
+#define RMIXL_DRAM_BAR_BASE_ADDR __BITS(31,16) /* bits 39:24 of Base Address */
+#define DRAM_BAR_TO_BASE(r) \
+ (((r) & RMIXL_DRAM_BAR_BASE_ADDR) << (24 - 16))
+#define RMIXL_DRAM_BAR_ADDR_MASK __BITS(15,4) /* bits 35:24 of Address Mask */
+#define DRAM_BAR_TO_SIZE(r) \
+ ((((r) & RMIXL_DRAM_BAR_ADDR_MASK) + __BIT(4)) << (24 - 4))
+#define RMIXL_DRAM_BAR_INTERLEAVE __BITS(3,1) /* Interleave Mode */
+#define RMIXL_DRAM_BAR_STATUS __BIT(0) /* 1='region enabled' */
+
+/*
+ * RMIXL_SBC_DRAM_CHNAC_DTR and
+ * RMIXL_SBC_DRAM_CHNBD_DTR bit defines
+ * insert 'divisions' (0, 1 or 2) bits
+ * of value 'partition'
+ * at 'position' bit location.
+ */
+#define RMIXL_DRAM_DTR_RESa __BITS(31,14)
+#define RMIXL_DRAM_DTR_PARTITION __BITS(13,12)
+#define RMIXL_DRAM_DTR_RESb __BITS(11,10)
+#define RMIXL_DRAM_DTR_DIVISIONS __BITS(9,8)
+#define RMIXL_DRAM_DTR_RESc __BITS(7,6)
+#define RMIXL_DRAM_DTR_POSITION __BITS(5,0)
+#define RMIXL_DRAM_DTR_RESV \
+ (RMIXL_DRAM_DTR_RESa|RMIXL_DRAM_DTR_RESb|RMIXL_DRAM_DTR_RESc)
+
+/*
+ * RMIXL_SBC_DRAM_BRIDGE_CFG bit defines
+ */
+#define RMIXL_DRAM_CFG_RESa __BITS(31,13)
+#define RMIXL_DRAM_CFG_CHANNEL_MODE __BIT(12)
+#define RMIXL_DRAM_CFG_RESb __BIT(11)
+#define RMIXL_DRAM_CFG_INTERLEAVE_MODE __BITS(10,8)
+#define RMIXL_DRAM_CFG_RESc __BITS(7,5)
+#define RMIXL_DRAM_CFG_BUS_MODE __BIT(4)
+#define RMIXL_DRAM_CFG_RESd __BITS(3,2)
+#define RMIXL_DRAM_CFG_DRAM_MODE __BITS(1,0) /* 1=DDR2 */
+
+/*
+ * RMIXL_SBC_PCIE_CFG_BAR bit defines
+ */
+#define RMIXL_PCIE_CFG_BAR_BASE __BITS(31,17) /* phys address bits 39:25 */
+#define RMIXL_PCIE_CFG_BAR_BA_SHIFT (25 - 17)
+#define RMIXL_PCIE_CFG_BAR_TO_BA(r) \
+ (((r) & RMIXL_PCIE_CFG_BAR_BASE) << RMIXL_PCIE_CFG_BAR_BA_SHIFT)
+#define RMIXL_PCIE_CFG_BAR_RESV __BITS(16,1) /* (reserved) */
+#define RMIXL_PCIE_CFG_BAR_ENB __BIT(0) /* 1=Enable */
+#define RMIXL_PCIE_CFG_SIZE __BIT(25)
+#define RMIXL_PCIE_CFG_BAR(ba, en) \
+ ((uint32_t)(((ba) >> (25 - 17)) | ((en) ? RMIXL_PCIE_CFG_BAR_ENB : 0)))
+
+/*
+ * RMIXL_SBC_PCIE_ECFG_BAR bit defines
+ * (PCIe extended config space)
+ */
+#define RMIXL_PCIE_ECFG_BAR_BASE __BITS(31,21) /* phys address bits 39:29 */
+#define RMIXL_PCIE_ECFG_BAR_BA_SHIFT (29 - 21)
+#define RMIXL_PCIE_ECFG_BAR_TO_BA(r) \
+ (((r) & RMIXL_PCIE_ECFG_BAR_BASE) << RMIXL_PCIE_ECFG_BAR_BA_SHIFT)
+#define RMIXL_PCIE_ECFG_BAR_RESV __BITS(20,1) /* (reserved) */
+#define RMIXL_PCIE_ECFG_BAR_ENB __BIT(0) /* 1=Enable */
+#define RMIXL_PCIE_ECFG_SIZE __BIT(29)
+#define RMIXL_PCIE_ECFG_BAR(ba, en) \
+ ((uint32_t)(((ba) >> (29 - 21)) | ((en) ? RMIXL_PCIE_ECFG_BAR_ENB : 0)))
+
+/*
+ * RMIXL_SBC_PCIE_MEM_BAR bit defines
+ */
+#define RMIXL_PCIE_MEM_BAR_BASE __BITS(31,16) /* phys address bits 39:24 */
+#define RMIXL_PCIE_MEM_BAR_TO_BA(r) \
+ (((r) & RMIXL_PCIE_MEM_BAR_BASE) << (24 - 16))
+#define RMIXL_PCIE_MEM_BAR_MASK __BITS(15,1) /* phys address mask bits 38:24 */
+#define RMIXL_PCIE_MEM_BAR_TO_SIZE(r) \
+ ((((r) & RMIXL_PCIE_MEM_BAR_MASK) + 2) << (24 - 1))
+#define RMIXL_PCIE_MEM_BAR_ENB __BIT(0) /* 1=Enable */
+#define RMIXL_PCIE_MEM_BAR(ba, en) \
+ ((uint32_t)(((ba) >> (24 - 16)) | ((en) ? RMIXL_PCIE_MEM_BAR_ENB : 0)))
+
+/*
+ * RMIXL_SBC_PCIE_IO_BAR bit defines
+ */
+#define RMIXL_PCIE_IO_BAR_BASE __BITS(31,18) /* phys address bits 39:26 */
+#define RMIXL_PCIE_IO_BAR_TO_BA(r) \
+ (((r) & RMIXL_PCIE_IO_BAR_BASE) << (26 - 18))
+#define RMIXL_PCIE_IO_BAR_RESV __BITS(17,7) /* (reserve) */
+#define RMIXL_PCIE_IO_BAR_MASK __BITS(6,1) /* phys address mask bits 31:26 */
+#define RMIXL_PCIE_IO_BAR_TO_SIZE(r) \
+ ((((r) & RMIXL_PCIE_IO_BAR_MASK) + 2) << (26 - 1))
+#define RMIXL_PCIE_IO_BAR_ENB __BIT(0) /* 1=Enable */
+#define RMIXL_PCIE_IO_BAR(ba, en) \
+ ((uint32_t)(((ba) >> (26 - 18)) | ((en) ? RMIXL_PCIE_IO_BAR_ENB : 0)))
+
+
+/*
+ * Programmable Interrupt Controller registers
+ * the Programming Reference Manual table 10.4
+ * lists "Reg ID" values not offsets
+ * Offsets are relative to RMIXL_IO_DEV_BRIDGE
+ */
#define RMIXL_PIC_CONTROL _RMIXL_OFFSET(0x0)
#define RMIXL_PIC_IPIBASE _RMIXL_OFFSET(0x4)
-#define RMIXL_PIC_RMIXL_OFFSET _RMIXL_OFFSET(0x6)
+#define RMIXL_PIC_INTRACK _RMIXL_OFFSET(0x6)
#define RMIXL_PIC_WATCHdOGMAXVALUE0 _RMIXL_OFFSET(0x8)
#define RMIXL_PIC_WATCHDOGMAXVALUE1 _RMIXL_OFFSET(0x9)
#define RMIXL_PIC_WATCHDOGMASK0 _RMIXL_OFFSET(0xa)
@@ -226,7 +383,10 @@
* IRT Entry low word
*/
#define RMIXL_PIC_IRTENTRYC0_TMASK __BITS(7,0) /* Thread Mask */
-#define RMIXL_PIC_IRTENTRYC0_RESV __BITS(31,8)
+#define RMIXL_PIC_IRTENTRYC0_RESa __BITS(3,2) /* write as 0 */
+#define RMIXL_PIC_IRTENTRYC0_RESb __BITS(31,8) /* write as 0 */
+#define RMIXL_PIC_IRTENTRYC0_RESV \
+ (RMIXL_PIC_IRTENTRYC0_RESa | RMIXL_PIC_IRTENTRYC0_RESb)
/*
* RMIXL_PIC_IRTENTRYC1 bits
@@ -241,6 +401,120 @@
#define RMIXL_PIC_IRTENTRYC1_VALID __BIT(31) /* 0=Invalid; 1=Valid IRT Entry */
+/*
+ * GPIO Controller registers
+ */
+
+/* GPIO Signal Registers */
+#define RMIXL_GPIO_INT_ENB _RMIXL_OFFSET(0x0) /* Interrupt Enable register */
+#define RMIXL_GPIO_INT_INV _RMIXL_OFFSET(0x1) /* Interrupt Inversion register */
+#define RMIXL_GPIO_IO_DIR _RMIXL_OFFSET(0x2) /* I/O Direction register */
+#define RMIXL_GPIO_OUTPUT _RMIXL_OFFSET(0x3) /* Output Write register */
+#define RMIXL_GPIO_INPUT _RMIXL_OFFSET(0x4) /* Intput Read register */
+#define RMIXL_GPIO_INT_CLR _RMIXL_OFFSET(0x5) /* Interrupt Inversion register */
+#define RMIXL_GPIO_INT_STS _RMIXL_OFFSET(0x6) /* Interrupt Status register */
+#define RMIXL_GPIO_INT_TYP _RMIXL_OFFSET(0x7) /* Interrupt Type register */
+#define RMIXL_GPIO_RESET _RMIXL_OFFSET(0x8) /* XLS Soft Reset register */
+
+/* GPIO System Control Registers */
+#define RMIXL_GPIO_RESET_CFG _RMIXL_OFFSET(0x15) /* Reset Configuration register */
+#define RMIXL_GPIO_THERMAL_CSR _RMIXL_OFFSET(0x16) /* Thermal Control/Status register */
+#define RMIXL_GPIO_THERMAL_SHFT _RMIXL_OFFSET(0x17) /* Thermal Shift register */
+#define RMIXL_GPIO_BIST_ALL_STS _RMIXL_OFFSET(0x18) /* BIST All Status register */
+#define RMIXL_GPIO_BIST_EACH_STS _RMIXL_OFFSET(0x19) /* BIST Each Status register */
+#define RMIXL_GPIO_SGMII_0_3_PHY_CTL _RMIXL_OFFSET(0x20) /* SGMII #0..3 PHY Control register */
+#define RMIXL_GPIO_AUI_0_PHY_CTL _RMIXL_OFFSET(0x20) /* AUI port#0 PHY Control register */
+#define RMIXL_GPIO_SGMII_4_7_PLL_CTL _RMIXL_OFFSET(0x21) /* SGMII #4..7 PLL Control register */
+#define RMIXL_GPIO_AUI_1_PLL_CTL _RMIXL_OFFSET(0x21) /* AUI port#1 PLL Control register */
+#define RMIXL_GPIO_SGMII_4_7_PHY_CTL _RMIXL_OFFSET(0x22) /* SGMII #4..7 PHY Control register */
+#define RMIXL_GPIO_AUI_1_PHY_CTL _RMIXL_OFFSET(0x22) /* AUI port#1 PHY Control register */
+#define RMIXL_GPIO_INT_MAP _RMIXL_OFFSET(0x25) /* Interrupt Map to PIC, 0=int14, 1=int30 */
+#define RMIXL_GPIO_EXT_INT _RMIXL_OFFSET(0x26) /* External Interrupt control register */
+#define RMIXL_GPIO_CPU_RST _RMIXL_OFFSET(0x28) /* CPU Reset control register */
+#define RMIXL_GPIO_LOW_PWR_DIS _RMIXL_OFFSET(0x29) /* Low Power Dissipation register */
+#define RMIXL_GPIO_RANDOM _RMIXL_OFFSET(0x2b) /* Low Power Dissipation register */
+#define RMIXL_GPIO_CPU_CLK_DIS _RMIXL_OFFSET(0x2d) /* CPU Clock Disable register */
+
+/*
+ * PCIE Interface Controller registers
+ */
+#define RMIXL_PCIE_CTRL1 _RMIXL_OFFSET(0x0)
+#define RMIXL_PCIE_CTRL2 _RMIXL_OFFSET(0x1)
+#define RMIXL_PCIE_CTRL3 _RMIXL_OFFSET(0x2)
+#define RMIXL_PCIE_CTRL4 _RMIXL_OFFSET(0x3)
+#define RMIXL_PCIE_CTRL _RMIXL_OFFSET(0x4)
+#define RMIXL_PCIE_IOBM_TIMER _RMIXL_OFFSET(0x5)
+#define RMIXL_PCIE_MSI_CMD _RMIXL_OFFSET(0x6)
+#define RMIXL_PCIE_MSI_RESP _RMIXL_OFFSET(0x7)
+#define RMIXL_PCIE_DWC_CRTL5 _RMIXL_OFFSET(0x8) /* not on XLS408Lite, XLS404Lite */
+#define RMIXL_PCIE_DWC_CRTL6 _RMIXL_OFFSET(0x9) /* not on XLS408Lite, XLS404Lite */
+#define RMIXL_PCIE_IOBM_SWAP_MEM_BASE _RMIXL_OFFSET(0x10)
+#define RMIXL_PCIE_IOBM_SWAP_MEM_LIMIT _RMIXL_OFFSET(0x11)
+#define RMIXL_PCIE_IOBM_SWAP_IO_BASE _RMIXL_OFFSET(0x12)
+#define RMIXL_PCIE_IOBM_SWAP_IO_LIMIT _RMIXL_OFFSET(0x13)
+#define RMIXL_PCIE_TRGT_CHRNT_MEM_BASE _RMIXL_OFFSET(0x14)
+#define RMIXL_PCIE_TRGT_CHRNT_MEM_LIMIT _RMIXL_OFFSET(0x15)
+#define RMIXL_PCIE_TRGT_L2ALC_MEM_BASE _RMIXL_OFFSET(0x16)
+#define RMIXL_PCIE_TRGT_L2ALC_MEM_LIMIT _RMIXL_OFFSET(0x17)
+#define RMIXL_PCIE_TRGT_REX_MEM_BASE _RMIXL_OFFSET(0x18)
+#define RMIXL_PCIE_TRGT_REX_MEM_LIMIT _RMIXL_OFFSET(0x19)
+#define RMIXL_PCIE_EP_MEM_BASE _RMIXL_OFFSET(0x1a)
+#define RMIXL_PCIE_EP_MEM_LIMIT _RMIXL_OFFSET(0x1b)
+#define RMIXL_PCIE_EP_ADDR_MAP_ENTRY0 _RMIXL_OFFSET(0x1c)
+#define RMIXL_PCIE_EP_ADDR_MAP_ENTRY1 _RMIXL_OFFSET(0x1d)
+#define RMIXL_PCIE_EP_ADDR_MAP_ENTRY2 _RMIXL_OFFSET(0x1e)
+#define RMIXL_PCIE_EP_ADDR_MAP_ENTRY3 _RMIXL_OFFSET(0x1f)
+#define RMIXL_PCIE_LINK0_STATE _RMIXL_OFFSET(0x20)
+#define RMIXL_PCIE_LINK1_STATE _RMIXL_OFFSET(0x21)
+#define RMIXL_PCIE_IOBM_INT_STATUS _RMIXL_OFFSET(0x22)
+#define RMIXL_PCIE_IOBM_INT_ENABLE _RMIXL_OFFSET(0x23)
+#define RMIXL_PCIE_LINK0_MSI_STATUS _RMIXL_OFFSET(0x24)
+#define RMIXL_PCIE_LINK1_MSI_STATUS _RMIXL_OFFSET(0x25)
+#define RMIXL_PCIE_LINK0_MSI_ENABLE _RMIXL_OFFSET(0x26)
+#define RMIXL_PCIE_LINK1_MSI_ENABLE _RMIXL_OFFSET(0x27)
+#define RMIXL_PCIE_LINK0_INT_STATUS0 _RMIXL_OFFSET(0x28)
+#define RMIXL_PCIE_LINK1_INT_STATUS0 _RMIXL_OFFSET(0x29)
+#define RMIXL_PCIE_LINK0_INT_STATUS1 _RMIXL_OFFSET(0x2a)
+#define RMIXL_PCIE_LINK1_INT_STATUS1 _RMIXL_OFFSET(0x2b)
+#define RMIXL_PCIE_LINK0_INT_ENABLE0 _RMIXL_OFFSET(0x2c)
+#define RMIXL_PCIE_LINK1_INT_ENABLE0 _RMIXL_OFFSET(0x2d)
+#define RMIXL_PCIE_LINK0_INT_ENABLE1 _RMIXL_OFFSET(0x2e)
+#define RMIXL_PCIE_LINK1_INT_ENABLE1 _RMIXL_OFFSET(0x2f)
+#define RMIXL_PCIE_PHY_CR_CMD _RMIXL_OFFSET(0x30)
+#define RMIXL_PCIE_PHY_CR_WR_DATA _RMIXL_OFFSET(0x31)
+#define RMIXL_PCIE_PHY_CR_RESP _RMIXL_OFFSET(0x32)
+#define RMIXL_PCIE_PHY_CR_RD_DATA _RMIXL_OFFSET(0x33)
+#define RMIXL_PCIE_IOBM_ERR_CMD _RMIXL_OFFSET(0x34)
+#define RMIXL_PCIE_IOBM_ERR_LOWER_ADDR _RMIXL_OFFSET(0x35)
+#define RMIXL_PCIE_IOBM_ERR_UPPER_ADDR _RMIXL_OFFSET(0x36)
+#define RMIXL_PCIE_IOBM_ERR_BE _RMIXL_OFFSET(0x37)
+#define RMIXL_PCIE_LINK2_STATE _RMIXL_OFFSET(0x60) /* not on XLS408Lite, XLS404Lite */
+#define RMIXL_PCIE_LINK3_STATE _RMIXL_OFFSET(0x61) /* not on XLS408Lite, XLS404Lite */
+#define RMIXL_PCIE_LINK2_MSI_STATUS _RMIXL_OFFSET(0x64) /* not on XLS408Lite, XLS404Lite */
+#define RMIXL_PCIE_LINK3_MSI_STATUS _RMIXL_OFFSET(0x65) /* not on XLS408Lite, XLS404Lite */
+#define RMIXL_PCIE_LINK2_MSI_ENABLE _RMIXL_OFFSET(0x66) /* not on XLS408Lite, XLS404Lite */
+#define RMIXL_PCIE_LINK3_MSI_ENABLE _RMIXL_OFFSET(0x67) /* not on XLS408Lite, XLS404Lite */
+#define RMIXL_PCIE_LINK2_INT_STATUS0 _RMIXL_OFFSET(0x68) /* not on XLS408Lite, XLS404Lite */
+#define RMIXL_PCIE_LINK3_INT_STATUS0 _RMIXL_OFFSET(0x69) /* not on XLS408Lite, XLS404Lite */
+#define RMIXL_PCIE_LINK2_INT_STATUS1 _RMIXL_OFFSET(0x6a) /* not on XLS408Lite, XLS404Lite */
+#define RMIXL_PCIE_LINK3_INT_STATUS1 _RMIXL_OFFSET(0x6b) /* not on XLS408Lite, XLS404Lite */
+#define RMIXL_PCIE_LINK2_INT_ENABLE0 _RMIXL_OFFSET(0x6c) /* not on XLS408Lite, XLS404Lite */
+#define RMIXL_PCIE_LINK3_INT_ENABLE0 _RMIXL_OFFSET(0x6d) /* not on XLS408Lite, XLS404Lite */
+#define RMIXL_PCIE_LINK2_INT_ENABLE1 _RMIXL_OFFSET(0x6e) /* not on XLS408Lite, XLS404Lite */
+#define RMIXL_PCIE_LINK3_INT_ENABLE1 _RMIXL_OFFSET(0x6f) /* not on XLS408Lite, XLS404Lite */
+#define RMIXL_VC0_POSTED_RX_QUEUE_CTRL _RMIXL_OFFSET(0x1d2)
+#define RMIXL_VC0_POSTED_BUFFER_DEPTH _RMIXL_OFFSET(0x1ea)
+#define RMIXL_PCIE_MSG_TX_THRESHOLD _RMIXL_OFFSET(0x308)
+#define RMIXL_PCIE_MSG_BUCKET_SIZE_0 _RMIXL_OFFSET(0x320)
+#define RMIXL_PCIE_MSG_BUCKET_SIZE_1 _RMIXL_OFFSET(0x321)
+#define RMIXL_PCIE_MSG_BUCKET_SIZE_2 _RMIXL_OFFSET(0x322)
+#define RMIXL_PCIE_MSG_BUCKET_SIZE_3 _RMIXL_OFFSET(0x323)
+#define RMIXL_PCIE_MSG_BUCKET_SIZE_4 _RMIXL_OFFSET(0x324) /* not on XLS408Lite, XLS404Lite */
+#define RMIXL_PCIE_MSG_BUCKET_SIZE_5 _RMIXL_OFFSET(0x325) /* not on XLS408Lite, XLS404Lite */
+#define RMIXL_PCIE_MSG_BUCKET_SIZE_6 _RMIXL_OFFSET(0x326) /* not on XLS408Lite, XLS404Lite */
+#define RMIXL_PCIE_MSG_BUCKET_SIZE_7 _RMIXL_OFFSET(0x327) /* not on XLS408Lite, XLS404Lite */
+#define RMIXL_PCIE_MSG_CREDIT_FIRST _RMIXL_OFFSET(0x380)
+#define RMIXL_PCIE_MSG_CREDIT_LAST _RMIXL_OFFSET(0x3ff)
#endif /* _MIPS_RMI_RMIRMIXLEGS_H_ */
