Module Name: src
Committed By: jmcneill
Date: Thu Aug 9 10:27:17 UTC 2018
Modified Files:
src/sys/arch/aarch64/include: armreg.h
Log Message:
Restore ICC_SRE_EL2 registers lost in previous commit
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/aarch64/include/armreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/include/armreg.h
diff -u src/sys/arch/aarch64/include/armreg.h:1.15 src/sys/arch/aarch64/include/armreg.h:1.16
--- src/sys/arch/aarch64/include/armreg.h:1.15 Wed Aug 8 19:00:53 2018
+++ src/sys/arch/aarch64/include/armreg.h Thu Aug 9 10:27:17 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.15 2018/08/08 19:00:53 jmcneill Exp $ */
+/* $NetBSD: armreg.h,v 1.16 2018/08/09 10:27:17 jmcneill Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -976,6 +976,12 @@ AARCH64REG_READ_INLINE2(icc_iar1_el1, s3
#define ICC_SRE_EL1_DFB __BIT(1)
#define ICC_SRE_EL1_SRE __BIT(0)
+// ICC_SRE_EL2: Interrupt Controller System Register Enable register
+#define ICC_SRE_EL2_EN __BIT(3)
+#define ICC_SRE_EL2_DIB __BIT(2)
+#define ICC_SRE_EL2_DFB __BIT(1)
+#define ICC_SRE_EL2_SRE __BIT(0)
+
// ICC_BPR[01]_EL1: Interrupt Controller Binary Point Register 0/1
#define ICC_BPR_EL1_BinaryPoint __BITS(2,0)
