Module Name:    src
Committed By:   skrll
Date:           Sun Aug 12 17:21:36 UTC 2018

Modified Files:
        src/sys/arch/aarch64/include: armreg.h
        src/sys/arch/arm/fdt: psci_fdt.c
        src/sys/arch/arm/include: armreg.h

Log Message:
Provide and use cpu_mpidr_aff_read in psci_fdt_bootstrap


To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/aarch64/include/armreg.h
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/fdt/psci_fdt.c
cvs rdiff -u -r1.122 -r1.123 src/sys/arch/arm/include/armreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/include/armreg.h
diff -u src/sys/arch/aarch64/include/armreg.h:1.17 src/sys/arch/aarch64/include/armreg.h:1.18
--- src/sys/arch/aarch64/include/armreg.h:1.17	Sun Aug 12 17:16:18 2018
+++ src/sys/arch/aarch64/include/armreg.h	Sun Aug 12 17:21:35 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.17 2018/08/12 17:16:18 skrll Exp $ */
+/* $NetBSD: armreg.h,v 1.18 2018/08/12 17:21:35 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -1025,6 +1025,19 @@ AARCH64REG_READ_INLINE2(icc_iar1_el1, s3
 #define	icc_iar1_read		reg_icc_iar1_el1_read
 #define	icc_eoi1r_write		reg_icc_eoir1_el1_write
 
+#if defined(_KERNEL)
+
+/*
+ * CPU REGISTER ACCESS
+ */
+static __inline register_t
+cpu_mpidr_aff_read(void)
+{
+
+	return reg_mpidr_el1_read() &
+	    (MPIDR_AFF3|MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0);
+}
+
 /*
  * GENERIC TIMER REGISTER ACCESS
  */
@@ -1117,5 +1130,6 @@ gtmr_cntv_cval_read(void)
 
 	return reg_cntv_cval_el0_read();
 }
+#endif /* _KERNEL */
 
 #endif /* _AARCH64_ARMREG_H_ */

Index: src/sys/arch/arm/fdt/psci_fdt.c
diff -u src/sys/arch/arm/fdt/psci_fdt.c:1.11 src/sys/arch/arm/fdt/psci_fdt.c:1.12
--- src/sys/arch/arm/fdt/psci_fdt.c:1.11	Fri Aug 10 22:34:36 2018
+++ src/sys/arch/arm/fdt/psci_fdt.c	Sun Aug 12 17:21:36 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: psci_fdt.c,v 1.11 2018/08/10 22:34:36 jmcneill Exp $ */
+/* $NetBSD: psci_fdt.c,v 1.12 2018/08/12 17:21:36 skrll Exp $ */
 
 /*-
  * Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca>
@@ -29,7 +29,7 @@
 #include "opt_multiprocessor.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: psci_fdt.c,v 1.11 2018/08/10 22:34:36 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: psci_fdt.c,v 1.12 2018/08/12 17:21:36 skrll Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -154,14 +154,6 @@ psci_fdt_preinit(void)
 }
 
 #ifdef MULTIPROCESSOR
-static bus_addr_t psci_fdt_read_mpidr_aff(void)
-{
-#ifdef __aarch64__
-	return reg_mpidr_el1_read() & (MPIDR_AFF3|MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0);
-#else
-	return armreg_mpidr_read() & (MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0);
-#endif
-}
 
 static register_t
 psci_fdt_mpstart_pa(void)
@@ -181,7 +173,7 @@ psci_fdt_bootstrap(void)
 {
 #ifdef MULTIPROCESSOR
 	extern void cortex_mpstart(void);
-	bus_addr_t mpidr, bp_mpidr;
+	uint64_t mpidr, bp_mpidr;
 	int child;
 
 	const int cpus = OF_finddevice("/cpus");
@@ -201,7 +193,7 @@ psci_fdt_bootstrap(void)
 		return;
 
 	/* MPIDR affinity levels of boot processor. */
-	bp_mpidr = psci_fdt_read_mpidr_aff();
+	bp_mpidr = cpu_mpidr_aff_read();
 
 	/* Boot APs */
 	uint32_t started = 0;

Index: src/sys/arch/arm/include/armreg.h
diff -u src/sys/arch/arm/include/armreg.h:1.122 src/sys/arch/arm/include/armreg.h:1.123
--- src/sys/arch/arm/include/armreg.h:1.122	Sun Jul 15 23:46:57 2018
+++ src/sys/arch/arm/include/armreg.h	Sun Aug 12 17:21:36 2018
@@ -1,4 +1,4 @@
-/*	$NetBSD: armreg.h,v 1.122 2018/07/15 23:46:57 jmcneill Exp $	*/
+/*	$NetBSD: armreg.h,v 1.123 2018/08/12 17:21:36 skrll Exp $	*/
 
 /*
  * Copyright (c) 1998, 2001 Ben Harris
@@ -908,6 +908,15 @@ ARMREG_WRITE_INLINE(tlbdataop, "p15,3,%0
 ARMREG_READ_INLINE(sheeva_xctrl, "p15,1,%0,c15,c1,0") /* Sheeva eXtra Control register */
 ARMREG_WRITE_INLINE(sheeva_xctrl, "p15,1,%0,c15,c1,0") /* Sheeva eXtra Control register */
 
+#if defined(_KERNEL)
+
+static inline uint64_t
+cpu_mpidr_aff_read(void)
+{
+
+	return armreg_mpidr_read() & (MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0);
+}
+
 /*
  * GENERIC TIMER register access
  */
@@ -1002,7 +1011,8 @@ gtmr_cntv_cval_read(void)
 	return armreg_cntv_cval_read();
 }
 
-#endif /* !__ASSEMBLER__ */
+#endif /* _KERNEL */
+#endif /* !__ASSEMBLER && !_RUMPKERNEL */
 
 #elif defined(__aarch64__)
 

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