Module Name: src
Committed By: jmcneill
Date: Fri Apr 19 19:07:56 UTC 2019
Modified Files:
src/sys/arch/arm/amlogic: files.meson meson_clk.c meson_dwmac.c
meson_pinctrl.c meson_pinctrl.h meson_platform.c mesongxbb_aoclkc.c
mesongxbb_clkc.c
src/sys/arch/evbarm/conf: GENERIC64
Added Files:
src/sys/arch/arm/amlogic: mesongxl_pinctrl.c mesongxl_usb2phy.c
mesongxl_usb3phy.c
Log Message:
Add support for Amlogic Meson GXL family SoCs.
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/amlogic/files.meson
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/amlogic/meson_clk.c \
src/sys/arch/arm/amlogic/meson_pinctrl.h
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/amlogic/meson_dwmac.c \
src/sys/arch/arm/amlogic/meson_pinctrl.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/amlogic/meson_platform.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/amlogic/mesongxbb_aoclkc.c \
src/sys/arch/arm/amlogic/mesongxbb_clkc.c
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/amlogic/mesongxl_pinctrl.c \
src/sys/arch/arm/amlogic/mesongxl_usb2phy.c \
src/sys/arch/arm/amlogic/mesongxl_usb3phy.c
cvs rdiff -u -r1.85 -r1.86 src/sys/arch/evbarm/conf/GENERIC64
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/amlogic/files.meson
diff -u src/sys/arch/arm/amlogic/files.meson:1.6 src/sys/arch/arm/amlogic/files.meson:1.7
--- src/sys/arch/arm/amlogic/files.meson:1.6 Fri Apr 5 12:11:26 2019
+++ src/sys/arch/arm/amlogic/files.meson Fri Apr 19 19:07:56 2019
@@ -1,4 +1,4 @@
-# $NetBSD: files.meson,v 1.6 2019/04/05 12:11:26 jmcneill Exp $
+# $NetBSD: files.meson,v 1.7 2019/04/19 19:07:56 jmcneill Exp $
#
# Configuration info for Amlogic Meson family SoCs
#
@@ -53,6 +53,7 @@ attach mesonpinctrl at fdt with meson_pi
file arch/arm/amlogic/meson_pinctrl.c meson_pinctrl
file arch/arm/amlogic/meson8b_pinctrl.c meson_pinctrl & soc_meson8b
file arch/arm/amlogic/mesongxbb_pinctrl.c meson_pinctrl & soc_mesongxbb
+file arch/arm/amlogic/mesongxl_pinctrl.c meson_pinctrl & soc_mesongxl
# Meson8b SDHC
device mesonsdhc: sdmmcbus
@@ -74,6 +75,16 @@ device mesonusbphy
attach mesonusbphy at fdt with meson_usbphy
file arch/arm/amlogic/meson_usbphy.c meson_usbphy
+# Meson GXL USB2 PHY
+device mesongxlu2phy
+attach mesongxlu2phy at fdt with mesongxl_usb2phy
+file arch/arm/amlogic/mesongxl_usb2phy.c mesongxl_usb2phy
+
+# Meson GXL USB3 PHY
+device mesongxlu3phy
+attach mesongxlu3phy at fdt with mesongxl_usb3phy
+file arch/arm/amlogic/mesongxl_usb3phy.c mesongxl_usb3phy
+
# RTC
device mesonrtc
attach mesonrtc at fdt with meson_rtc
@@ -96,4 +107,6 @@ file arch/arm/amlogic/meson_wdt.c meson
# SOC parameters
defflag opt_soc.h SOC_MESON
defflag opt_soc.h SOC_MESON8B: SOC_MESON
-defflag opt_soc.h SOC_MESONGXBB: SOC_MESON
+defflag opt_soc.h SOC_MESONGX: SOC_MESON
+defflag opt_soc.h SOC_MESONGXBB: SOC_MESONGX
+defflag opt_soc.h SOC_MESONGXL: SOC_MESONGX
Index: src/sys/arch/arm/amlogic/meson_clk.c
diff -u src/sys/arch/arm/amlogic/meson_clk.c:1.2 src/sys/arch/arm/amlogic/meson_clk.c:1.3
--- src/sys/arch/arm/amlogic/meson_clk.c:1.2 Mon Feb 25 19:30:17 2019
+++ src/sys/arch/arm/amlogic/meson_clk.c Fri Apr 19 19:07:56 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: meson_clk.c,v 1.2 2019/02/25 19:30:17 jmcneill Exp $ */
+/* $NetBSD: meson_clk.c,v 1.3 2019/04/19 19:07:56 jmcneill Exp $ */
/*-
* Copyright (c) 2017-2019 Jared McNeill <[email protected]>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: meson_clk.c,v 1.2 2019/02/25 19:30:17 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: meson_clk.c,v 1.3 2019/04/19 19:07:56 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -157,7 +157,7 @@ meson_clk_clock_get_rate(void *priv, str
clkp_parent = clk_get_parent(clkp);
if (clkp_parent == NULL) {
- aprint_error("%s: no parent for %s\n", __func__, clk->base.name);
+ aprint_debug("%s: no parent for %s\n", __func__, clk->base.name);
return 0;
}
@@ -174,7 +174,7 @@ meson_clk_clock_set_rate(void *priv, str
if (clkp->flags & CLK_SET_RATE_PARENT) {
clkp_parent = clk_get_parent(clkp);
if (clkp_parent == NULL) {
- aprint_error("%s: no parent for %s\n", __func__, clk->base.name);
+ aprint_debug("%s: no parent for %s\n", __func__, clk->base.name);
return ENXIO;
}
return clk_set_rate(clkp_parent, rate);
@@ -196,7 +196,7 @@ meson_clk_clock_round_rate(void *priv, s
if (clkp->flags & CLK_SET_RATE_PARENT) {
clkp_parent = clk_get_parent(clkp);
if (clkp_parent == NULL) {
- aprint_error("%s: no parent for %s\n", __func__, clk->base.name);
+ aprint_debug("%s: no parent for %s\n", __func__, clk->base.name);
return 0;
}
return clk_round_rate(clkp_parent, rate);
Index: src/sys/arch/arm/amlogic/meson_pinctrl.h
diff -u src/sys/arch/arm/amlogic/meson_pinctrl.h:1.2 src/sys/arch/arm/amlogic/meson_pinctrl.h:1.3
--- src/sys/arch/arm/amlogic/meson_pinctrl.h:1.2 Mon Feb 25 19:30:17 2019
+++ src/sys/arch/arm/amlogic/meson_pinctrl.h Fri Apr 19 19:07:56 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: meson_pinctrl.h,v 1.2 2019/02/25 19:30:17 jmcneill Exp $ */
+/* $NetBSD: meson_pinctrl.h,v 1.3 2019/04/19 19:07:56 jmcneill Exp $ */
/*-
* Copyright (c) 2019 Jared McNeill <[email protected]>
@@ -83,4 +83,9 @@ extern const struct meson_pinctrl_config
extern const struct meson_pinctrl_config mesongxbb_periphs_pinctrl_config;
#endif
+#ifdef SOC_MESONGXL
+extern const struct meson_pinctrl_config mesongxl_aobus_pinctrl_config;
+extern const struct meson_pinctrl_config mesongxl_periphs_pinctrl_config;
+#endif
+
#endif /* !_MESON_PINCTRL_H */
Index: src/sys/arch/arm/amlogic/meson_dwmac.c
diff -u src/sys/arch/arm/amlogic/meson_dwmac.c:1.4 src/sys/arch/arm/amlogic/meson_dwmac.c:1.5
--- src/sys/arch/arm/amlogic/meson_dwmac.c:1.4 Sat Mar 2 12:24:44 2019
+++ src/sys/arch/arm/amlogic/meson_dwmac.c Fri Apr 19 19:07:56 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: meson_dwmac.c,v 1.4 2019/03/02 12:24:44 jmcneill Exp $ */
+/* $NetBSD: meson_dwmac.c,v 1.5 2019/04/19 19:07:56 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <[email protected]>
@@ -28,7 +28,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: meson_dwmac.c,v 1.4 2019/03/02 12:24:44 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: meson_dwmac.c,v 1.5 2019/04/19 19:07:56 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -50,6 +50,7 @@ __KERNEL_RCSID(0, "$NetBSD: meson_dwmac.
#define PRG_ETHERNET_ADDR0 0x00
#define CLKGEN_ENABLE __BIT(12)
+#define RMII_CLK_I_INVERTED __BIT(11)
#define PHY_CLK_ENABLE __BIT(10)
#define MP2_CLK_OUT_DIV __BITS(9,7)
#define TX_CLK_DELAY __BITS(6,5)
@@ -114,6 +115,20 @@ meson_dwmac_set_mode_rgmii(int phandle,
bus_space_write_4(bst, bsh, PRG_ETHERNET_ADDR0, val);
}
+static void
+meson_dwmac_set_mode_rmii(int phandle, bus_space_tag_t bst,
+ bus_space_handle_t bsh)
+{
+ uint32_t val;
+
+ val = bus_space_read_4(bst, bsh, PRG_ETHERNET_ADDR0);
+ val &= ~PHY_INTERFACE_SEL;
+ val |= RMII_CLK_I_INVERTED;
+ val &= ~TX_CLK_DELAY;
+ val |= CLKGEN_ENABLE;
+ bus_space_write_4(bst, bsh, PRG_ETHERNET_ADDR0, val);
+}
+
static int
meson_dwmac_intr(void *arg)
{
@@ -182,6 +197,8 @@ meson_dwmac_attach(device_t parent, devi
if (strcmp(phy_mode, "rgmii") == 0) {
meson_dwmac_set_mode_rgmii(phandle, sc->sc_bst, prgeth_bsh, clk_in[0]);
+ } else if (strcmp(phy_mode, "rmii") == 0) {
+ meson_dwmac_set_mode_rmii(phandle, sc->sc_bst, prgeth_bsh);
} else {
aprint_error(": unsupported phy-mode '%s'\n", phy_mode);
return;
Index: src/sys/arch/arm/amlogic/meson_pinctrl.c
diff -u src/sys/arch/arm/amlogic/meson_pinctrl.c:1.4 src/sys/arch/arm/amlogic/meson_pinctrl.c:1.5
--- src/sys/arch/arm/amlogic/meson_pinctrl.c:1.4 Sat Mar 2 11:15:55 2019
+++ src/sys/arch/arm/amlogic/meson_pinctrl.c Fri Apr 19 19:07:56 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: meson_pinctrl.c,v 1.4 2019/03/02 11:15:55 jmcneill Exp $ */
+/* $NetBSD: meson_pinctrl.c,v 1.5 2019/04/19 19:07:56 jmcneill Exp $ */
/*-
* Copyright (c) 2019 Jared D. McNeill <[email protected]>
@@ -29,7 +29,7 @@
#include "opt_soc.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: meson_pinctrl.c,v 1.4 2019/03/02 11:15:55 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: meson_pinctrl.c,v 1.5 2019/04/19 19:07:56 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -80,6 +80,10 @@ static const struct of_compat_data compa
{ "amlogic,meson-gxbb-aobus-pinctrl", (uintptr_t)&mesongxbb_aobus_pinctrl_config },
{ "amlogic,meson-gxbb-periphs-pinctrl", (uintptr_t)&mesongxbb_periphs_pinctrl_config },
#endif
+#ifdef SOC_MESONGXL
+ { "amlogic,meson-gxl-aobus-pinctrl", (uintptr_t)&mesongxl_aobus_pinctrl_config },
+ { "amlogic,meson-gxl-periphs-pinctrl", (uintptr_t)&mesongxl_periphs_pinctrl_config },
+#endif
{ NULL, 0 }
};
Index: src/sys/arch/arm/amlogic/meson_platform.c
diff -u src/sys/arch/arm/amlogic/meson_platform.c:1.7 src/sys/arch/arm/amlogic/meson_platform.c:1.8
--- src/sys/arch/arm/amlogic/meson_platform.c:1.7 Fri Apr 5 12:07:02 2019
+++ src/sys/arch/arm/amlogic/meson_platform.c Fri Apr 19 19:07:56 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: meson_platform.c,v 1.7 2019/04/05 12:07:02 jmcneill Exp $ */
+/* $NetBSD: meson_platform.c,v 1.8 2019/04/19 19:07:56 jmcneill Exp $ */
/*-
* Copyright (c) 2019 Jared McNeill <[email protected]>
@@ -33,7 +33,7 @@
#include "arml2cc.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: meson_platform.c,v 1.7 2019/04/05 12:07:02 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: meson_platform.c,v 1.8 2019/04/19 19:07:56 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -446,8 +446,8 @@ static const struct arm_platform meson8b
ARM_PLATFORM(meson8b, "amlogic,meson8b", &meson8b_platform);
#endif /* SOC_MESON8B */
-#if defined(SOC_MESONGXBB)
-static const struct arm_platform mesongxbb_platform = {
+#if defined(SOC_MESONGX)
+static const struct arm_platform mesongx_platform = {
.ap_devmap = meson_platform_devmap,
.ap_bootstrap = meson_platform_bootstrap,
.ap_init_attach_args = meson_platform_init_attach_args,
@@ -458,5 +458,10 @@ static const struct arm_platform mesongx
.ap_mpstart = arm_fdt_cpu_mpstart,
};
-ARM_PLATFORM(mesongxbb, "amlogic,meson-gxbb", &mesongxbb_platform);
-#endif
+#if defined(SOC_MESONGXBB)
+ARM_PLATFORM(mesongxbb, "amlogic,meson-gxbb", &mesongx_platform);
+#endif /* SOC_MESONGXBB */
+#if defined(SOC_MESONGXL)
+ARM_PLATFORM(mesongxl, "amlogic,meson-gxl", &mesongx_platform);
+#endif /* SOC_MESONGXL */
+#endif /* SOC_MESONGX */
Index: src/sys/arch/arm/amlogic/mesongxbb_aoclkc.c
diff -u src/sys/arch/arm/amlogic/mesongxbb_aoclkc.c:1.1 src/sys/arch/arm/amlogic/mesongxbb_aoclkc.c:1.2
--- src/sys/arch/arm/amlogic/mesongxbb_aoclkc.c:1.1 Mon Feb 25 19:30:17 2019
+++ src/sys/arch/arm/amlogic/mesongxbb_aoclkc.c Fri Apr 19 19:07:56 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: mesongxbb_aoclkc.c,v 1.1 2019/02/25 19:30:17 jmcneill Exp $ */
+/* $NetBSD: mesongxbb_aoclkc.c,v 1.2 2019/04/19 19:07:56 jmcneill Exp $ */
/*-
* Copyright (c) 2019 Jared McNeill <[email protected]>
@@ -28,7 +28,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: mesongxbb_aoclkc.c,v 1.1 2019/02/25 19:30:17 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: mesongxbb_aoclkc.c,v 1.2 2019/04/19 19:07:56 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -49,6 +49,7 @@ static void mesongxbb_aoclkc_attach(devi
static const char * const compatible[] = {
"amlogic,meson-gxbb-aoclkc",
+ "amlogic,meson-gxl-aoclkc",
NULL
};
@@ -104,7 +105,7 @@ mesongxbb_aoclkc_attach(device_t parent,
meson_clk_attach(sc);
aprint_naive("\n");
- aprint_normal(": Meson GXBB AO clock controller\n");
+ aprint_normal(": Meson GX AO clock controller\n");
meson_clk_print(sc);
}
Index: src/sys/arch/arm/amlogic/mesongxbb_clkc.c
diff -u src/sys/arch/arm/amlogic/mesongxbb_clkc.c:1.1 src/sys/arch/arm/amlogic/mesongxbb_clkc.c:1.2
--- src/sys/arch/arm/amlogic/mesongxbb_clkc.c:1.1 Mon Feb 25 19:30:17 2019
+++ src/sys/arch/arm/amlogic/mesongxbb_clkc.c Fri Apr 19 19:07:56 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: mesongxbb_clkc.c,v 1.1 2019/02/25 19:30:17 jmcneill Exp $ */
+/* $NetBSD: mesongxbb_clkc.c,v 1.2 2019/04/19 19:07:56 jmcneill Exp $ */
/*-
* Copyright (c) 2019 Jared McNeill <[email protected]>
@@ -28,7 +28,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: mesongxbb_clkc.c,v 1.1 2019/02/25 19:30:17 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: mesongxbb_clkc.c,v 1.2 2019/04/19 19:07:56 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -66,9 +66,22 @@ __KERNEL_RCSID(1, "$NetBSD: mesongxbb_cl
static int mesongxbb_clkc_match(device_t, cfdata_t, void *);
static void mesongxbb_clkc_attach(device_t, device_t, void *);
-static const char * const compatible[] = {
- "amlogic,gxbb-clkc",
- NULL
+struct mesongxbb_clkc_config {
+ const char *name;
+};
+
+static const struct mesongxbb_clkc_config gxbb_config = {
+ .name = "Meson GXBB",
+};
+
+static const struct mesongxbb_clkc_config gxl_config = {
+ .name = "Meson GXL",
+};
+
+static const struct of_compat_data compat_data[] = {
+ { "amlogic,gxbb-clkc", (uintptr_t)&gxbb_config },
+ { "amlogic,gxl-clkc", (uintptr_t)&gxl_config },
+ { NULL }
};
CFATTACH_DECL_NEW(mesongxbb_clkc, sizeof(struct meson_clk_softc),
@@ -215,7 +228,7 @@ mesongxbb_clkc_match(device_t parent, cf
{
struct fdt_attach_args * const faa = aux;
- return of_match_compatible(faa->faa_phandle, compatible);
+ return of_match_compat_data(faa->faa_phandle, compat_data);
}
static void
@@ -223,6 +236,8 @@ mesongxbb_clkc_attach(device_t parent, d
{
struct meson_clk_softc * const sc = device_private(self);
struct fdt_attach_args * const faa = aux;
+ const struct mesongxbb_clkc_config *conf;
+ const int phandle = faa->faa_phandle;
sc->sc_dev = self;
sc->sc_phandle = faa->faa_phandle;
@@ -237,8 +252,10 @@ mesongxbb_clkc_attach(device_t parent, d
meson_clk_attach(sc);
+ conf = (const void *)of_search_compatible(phandle, compat_data)->data;
+
aprint_naive("\n");
- aprint_normal(": Meson GXBB clock controller\n");
+ aprint_normal(": %s clock controller\n", conf->name);
meson_clk_print(sc);
}
Index: src/sys/arch/evbarm/conf/GENERIC64
diff -u src/sys/arch/evbarm/conf/GENERIC64:1.85 src/sys/arch/evbarm/conf/GENERIC64:1.86
--- src/sys/arch/evbarm/conf/GENERIC64:1.85 Sun Apr 7 13:50:29 2019
+++ src/sys/arch/evbarm/conf/GENERIC64 Fri Apr 19 19:07:55 2019
@@ -1,5 +1,5 @@
#
-# $NetBSD: GENERIC64,v 1.85 2019/04/07 13:50:29 jmcneill Exp $
+# $NetBSD: GENERIC64,v 1.86 2019/04/19 19:07:55 jmcneill Exp $
#
# GENERIC ARM (aarch64) kernel
#
@@ -31,6 +31,17 @@ makeoptions DTS="
meson-gxbb-wetek-hub.dts
meson-gxbb-wetek-play2.dts
+ meson-gxl-s805x-p241.dts
+ meson-gxl-s905d-p230.dts
+ meson-gxl-s905d-p231.dts
+ meson-gxl-s905w-p281.dts
+ meson-gxl-s905w-tx3-mini.dts
+ meson-gxl-s905x-hwacom-amazetv.dts
+ meson-gxl-s905x-khadas-vim.dts
+ meson-gxl-s905x-libretech-cc.dts
+ meson-gxl-s905x-nexbox-a95x.dts
+ meson-gxl-s905x-p212.dts
+
rk3328-evb.dts
rk3328-roc-cc.dts
rk3328-rock64.dts
@@ -80,6 +91,7 @@ options CPU_CORTEXA57
options CPU_THUNDERX
options SOC_BCM2837
options SOC_MESONGXBB
+options SOC_MESONGXL
options SOC_RK3328
options SOC_RK3399
options SOC_SUN50I_A64
@@ -206,7 +218,7 @@ tegrapmc* at fdt? pass 4 # NVIDIA Tegra
bcmcprman* at fdt? pass 1 # Broadcom BCM283x Clock Manager
bcmaux* at fdt? pass 1 # Broadcom BCM283x Aux Periph Clocks
gxbbaoclkc* at fdt? pass 2 # Amlogic Meson GXBB AO clock controller
-gxbbclkc* at fdt? pass 2 # Amlogic Meson GXBB EE clock controller
+gxbbclkc* at fdt? pass 2 # Amlogic Meson GXBB/GXL EE clock controller
mesonresets* at fdt? pass 2 # Amlogic Meson misc. clock resets
rkcru* at fdt? pass 2 # Rockchip RK3328 CRU
sun8ih3ccu* at fdt? pass 2 # Allwinner H3/H5 CCU
@@ -429,6 +441,8 @@ tegrasoctherm* at fdt? # NVIDIA Tegra
# USB
mesonusbphy* at fdt? pass 9 # Amlogic Meson USB2 PHY
+mesongxlu2phy* at fdt? pass 9 # Amlogic Meson GXL USB2 PHY
+mesongxlu3phy* at fdt? pass 9 # Amlogic Meson GXL USB3 PHY
rkusb* at fdt? pass 9 # Rockchip USB PHY
rkusbphy* at rkusb?
sunxiusbphy* at fdt? pass 9 # Allwinner USB PHY
Added files:
Index: src/sys/arch/arm/amlogic/mesongxl_pinctrl.c
diff -u /dev/null src/sys/arch/arm/amlogic/mesongxl_pinctrl.c:1.1
--- /dev/null Fri Apr 19 19:07:56 2019
+++ src/sys/arch/arm/amlogic/mesongxl_pinctrl.c Fri Apr 19 19:07:56 2019
@@ -0,0 +1,483 @@
+/* $NetBSD: mesongxl_pinctrl.c,v 1.1 2019/04/19 19:07:56 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2019 Jared McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: mesongxl_pinctrl.c,v 1.1 2019/04/19 19:07:56 jmcneill Exp $");
+
+#include <sys/param.h>
+
+#include <arm/amlogic/meson_pinctrl.h>
+
+/* CBUS pinmux registers */
+#define CBUS_REG(n) ((n) << 2)
+#define REG0 CBUS_REG(0)
+#define REG1 CBUS_REG(1)
+#define REG2 CBUS_REG(2)
+#define REG3 CBUS_REG(3)
+#define REG4 CBUS_REG(4)
+#define REG5 CBUS_REG(5)
+#define REG6 CBUS_REG(6)
+#define REG7 CBUS_REG(7)
+#define REG8 CBUS_REG(8)
+#define REG9 CBUS_REG(9)
+
+/* AO pinmux registers */
+#define AOREG0 0x00
+#define AOREG1 0x04
+
+/*
+ * GPIO banks. The values must match those in dt-bindings/gpio/meson-gxl-gpio.h
+ */
+enum {
+ GPIOZ_0 = 0,
+ GPIOZ_1,
+ GPIOZ_2,
+ GPIOZ_3,
+ GPIOZ_4,
+ GPIOZ_5,
+ GPIOZ_6,
+ GPIOZ_7,
+ GPIOZ_8,
+ GPIOZ_9,
+ GPIOZ_10,
+ GPIOZ_11,
+ GPIOZ_12,
+ GPIOZ_13,
+ GPIOZ_14,
+ GPIOZ_15,
+
+ GPIOH_0 = 16,
+ GPIOH_1,
+ GPIOH_2,
+ GPIOH_3,
+ GPIOH_4,
+ GPIOH_5,
+ GPIOH_6,
+ GPIOH_7,
+ GPIOH_8,
+ GPIOH_9,
+
+ BOOT_0 = 26,
+ BOOT_1,
+ BOOT_2,
+ BOOT_3,
+ BOOT_4,
+ BOOT_5,
+ BOOT_6,
+ BOOT_7,
+ BOOT_8,
+ BOOT_9,
+ BOOT_10,
+ BOOT_11,
+ BOOT_12,
+ BOOT_13,
+ BOOT_14,
+ BOOT_15,
+
+ CARD_0 = 42,
+ CARD_1,
+ CARD_2,
+ CARD_3,
+ CARD_4,
+ CARD_5,
+ CARD_6,
+
+ GPIODV_0 = 49,
+ GPIODV_1,
+ GPIODV_2,
+ GPIODV_3,
+ GPIODV_4,
+ GPIODV_5,
+ GPIODV_6,
+ GPIODV_7,
+ GPIODV_8,
+ GPIODV_9,
+ GPIODV_10,
+ GPIODV_11,
+ GPIODV_12,
+ GPIODV_13,
+ GPIODV_14,
+ GPIODV_15,
+ GPIODV_16,
+ GPIODV_17,
+ GPIODV_18,
+ GPIODV_19,
+ GPIODV_20,
+ GPIODV_21,
+ GPIODV_22,
+ GPIODV_23,
+ GPIODV_24,
+ GPIODV_25,
+ GPIODV_26,
+ GPIODV_27,
+ GPIODV_28,
+ GPIODV_29,
+
+ GPIOX_0 = 79,
+ GPIOX_1,
+ GPIOX_2,
+ GPIOX_3,
+ GPIOX_4,
+ GPIOX_5,
+ GPIOX_6,
+ GPIOX_7,
+ GPIOX_8,
+ GPIOX_9,
+ GPIOX_10,
+ GPIOX_11,
+ GPIOX_12,
+ GPIOX_13,
+ GPIOX_14,
+ GPIOX_15,
+ GPIOX_16,
+ GPIOX_17,
+ GPIOX_18,
+
+ GPIOCLK_0 = 98,
+ GPIOCLK_1,
+
+ GPIOAO_0 = 0,
+ GPIOAO_1,
+ GPIOAO_2,
+ GPIOAO_3,
+ GPIOAO_4,
+ GPIOAO_5,
+ GPIOAO_6,
+ GPIOAO_7,
+ GPIOAO_8,
+ GPIOAO_9,
+ GPIO_TEST_N,
+};
+
+#define CBUS_GPIO(_id, _off, _bit) \
+ [_id] = { \
+ .id = (_id), \
+ .name = __STRING(_id), \
+ .oen = { \
+ .type = MESON_PINCTRL_REGTYPE_GPIO, \
+ .reg = CBUS_REG((_off) * 3 + 0), \
+ .mask = __BIT(_bit) \
+ }, \
+ .out = { \
+ .type = MESON_PINCTRL_REGTYPE_GPIO, \
+ .reg = CBUS_REG((_off) * 3 + 1), \
+ .mask = __BIT(_bit) \
+ }, \
+ .in = { \
+ .type = MESON_PINCTRL_REGTYPE_GPIO, \
+ .reg = CBUS_REG((_off) * 3 + 2), \
+ .mask = __BIT(_bit) \
+ }, \
+ .pupden = { \
+ .type = MESON_PINCTRL_REGTYPE_PULL_ENABLE, \
+ .reg = CBUS_REG(_off), \
+ .mask = __BIT(_bit) \
+ }, \
+ .pupd = { \
+ .type = MESON_PINCTRL_REGTYPE_PULL, \
+ .reg = CBUS_REG(_off), \
+ .mask = __BIT(_bit) \
+ }, \
+ }
+
+static const struct meson_pinctrl_gpio mesongxl_periphs_gpios[] = {
+ /* GPIODV */
+ CBUS_GPIO(GPIODV_24, 0, 24),
+ CBUS_GPIO(GPIODV_25, 0, 25),
+ CBUS_GPIO(GPIODV_26, 0, 26),
+ CBUS_GPIO(GPIODV_27, 0, 27),
+ CBUS_GPIO(GPIODV_28, 0, 28),
+ CBUS_GPIO(GPIODV_29, 0, 29),
+
+ /* GPIOH */
+ CBUS_GPIO(GPIOH_0, 1, 20),
+ CBUS_GPIO(GPIOH_1, 1, 21),
+ CBUS_GPIO(GPIOH_2, 1, 22),
+ CBUS_GPIO(GPIOH_3, 1, 23),
+ CBUS_GPIO(GPIOH_4, 1, 24),
+ CBUS_GPIO(GPIOH_5, 1, 25),
+ CBUS_GPIO(GPIOH_6, 1, 26),
+ CBUS_GPIO(GPIOH_7, 1, 27),
+ CBUS_GPIO(GPIOH_8, 1, 28),
+ CBUS_GPIO(GPIOH_9, 1, 29),
+
+ /* BOOT */
+ CBUS_GPIO(BOOT_0, 2, 0),
+ CBUS_GPIO(BOOT_1, 2, 1),
+ CBUS_GPIO(BOOT_2, 2, 2),
+ CBUS_GPIO(BOOT_3, 2, 3),
+ CBUS_GPIO(BOOT_4, 2, 4),
+ CBUS_GPIO(BOOT_5, 2, 5),
+ CBUS_GPIO(BOOT_6, 2, 6),
+ CBUS_GPIO(BOOT_7, 2, 7),
+ CBUS_GPIO(BOOT_8, 2, 8),
+ CBUS_GPIO(BOOT_9, 2, 9),
+ CBUS_GPIO(BOOT_10, 2, 10),
+ CBUS_GPIO(BOOT_11, 2, 11),
+ CBUS_GPIO(BOOT_12, 2, 12),
+ CBUS_GPIO(BOOT_13, 2, 13),
+ CBUS_GPIO(BOOT_14, 2, 14),
+ CBUS_GPIO(BOOT_15, 2, 15),
+
+ /* CARD */
+ CBUS_GPIO(CARD_0, 2, 20),
+ CBUS_GPIO(CARD_1, 2, 21),
+ CBUS_GPIO(CARD_2, 2, 22),
+ CBUS_GPIO(CARD_3, 2, 23),
+ CBUS_GPIO(CARD_4, 2, 24),
+ CBUS_GPIO(CARD_5, 2, 25),
+ CBUS_GPIO(CARD_6, 2, 26),
+
+ /* GPIOCLK */
+ CBUS_GPIO(GPIOCLK_0, 3, 28),
+ CBUS_GPIO(GPIOCLK_1, 3, 29),
+
+ /* GPIOX */
+ CBUS_GPIO(GPIOX_0, 4, 0),
+ CBUS_GPIO(GPIOX_1, 4, 1),
+ CBUS_GPIO(GPIOX_2, 4, 2),
+ CBUS_GPIO(GPIOX_3, 4, 3),
+ CBUS_GPIO(GPIOX_4, 4, 4),
+ CBUS_GPIO(GPIOX_5, 4, 5),
+ CBUS_GPIO(GPIOX_6, 4, 6),
+ CBUS_GPIO(GPIOX_7, 4, 7),
+ CBUS_GPIO(GPIOX_8, 4, 8),
+ CBUS_GPIO(GPIOX_9, 4, 9),
+ CBUS_GPIO(GPIOX_10, 4, 10),
+ CBUS_GPIO(GPIOX_11, 4, 11),
+ CBUS_GPIO(GPIOX_12, 4, 12),
+ CBUS_GPIO(GPIOX_13, 4, 13),
+ CBUS_GPIO(GPIOX_14, 4, 14),
+ CBUS_GPIO(GPIOX_15, 4, 15),
+ CBUS_GPIO(GPIOX_16, 4, 16),
+ CBUS_GPIO(GPIOX_17, 4, 17),
+ CBUS_GPIO(GPIOX_18, 4, 18),
+};
+
+#define AO_GPIO(_id, _bit) \
+ [_id] = { \
+ .id = (_id), \
+ .name = __STRING(_id), \
+ .oen = { \
+ .type = MESON_PINCTRL_REGTYPE_GPIO, \
+ .reg = 0, \
+ .mask = __BIT(_bit) \
+ }, \
+ .out = { \
+ .type = MESON_PINCTRL_REGTYPE_GPIO, \
+ .reg = 0, \
+ .mask = __BIT(_bit + 16) \
+ }, \
+ .in = { \
+ .type = MESON_PINCTRL_REGTYPE_GPIO, \
+ .reg = 4, \
+ .mask = __BIT(_bit) \
+ }, \
+ .pupden = { \
+ .type = MESON_PINCTRL_REGTYPE_PULL, \
+ .reg = 0, \
+ .mask = __BIT(_bit) \
+ }, \
+ .pupd = { \
+ .type = MESON_PINCTRL_REGTYPE_PULL, \
+ .reg = 0, \
+ .mask = __BIT(_bit + 16) \
+ }, \
+ }
+
+static const struct meson_pinctrl_gpio mesongxl_aobus_gpios[] = {
+ /* GPIOAO */
+ AO_GPIO(GPIOAO_0, 0),
+ AO_GPIO(GPIOAO_1, 1),
+ AO_GPIO(GPIOAO_2, 2),
+ AO_GPIO(GPIOAO_3, 3),
+ AO_GPIO(GPIOAO_4, 4),
+ AO_GPIO(GPIOAO_5, 5),
+ AO_GPIO(GPIOAO_6, 6),
+ AO_GPIO(GPIOAO_7, 7),
+ AO_GPIO(GPIOAO_8, 8),
+ AO_GPIO(GPIOAO_9, 9),
+};
+
+static const struct meson_pinctrl_group mesongxl_periphs_groups[] = {
+ /* GPIOX */
+ { "sdio_d0", REG5, 31, { GPIOX_0 }, 1 },
+ { "sdio_d1", REG5, 30, { GPIOX_1 }, 1 },
+ { "sdio_d2", REG5, 29, { GPIOX_2 }, 1 },
+ { "sdio_d3", REG5, 28, { GPIOX_3 }, 1 },
+ { "sdio_clk", REG5, 27, { GPIOX_4 }, 1 },
+ { "sdio_cmd", REG5, 26, { GPIOX_5 }, 1 },
+ { "sdio_irq", REG5, 24, { GPIOX_7 }, 1 },
+ { "uart_tx_a", REG5, 19, { GPIOX_12 }, 1 },
+ { "uart_rx_a", REG5, 18, { GPIOX_13 }, 1 },
+ { "uart_cts_a", REG5, 17, { GPIOX_14 }, 1 },
+ { "uart_dts_a", REG5, 16, { GPIOX_15 }, 1 },
+ { "uart_tx_c", REG5, 13, { GPIOX_8 }, 1 },
+ { "uart_rx_c", REG5, 12, { GPIOX_9 }, 1 },
+ { "uart_cts_c", REG5, 11, { GPIOX_10 }, 1 },
+ { "uart_dts_c", REG5, 10, { GPIOX_11 }, 1 },
+ { "pwm_a", REG5, 25, { GPIOX_6 }, 1 },
+ { "pwm_e", REG5, 15, { GPIOX_16 }, 1 },
+ { "pwm_f_x", REG5, 14, { GPIOX_7 }, 1 },
+ { "spi_mosi", REG5, 3, { GPIOX_8 }, 1 },
+ { "spi_miso", REG5, 2, { GPIOX_9 }, 1 },
+ { "spi_ss0", REG5, 1, { GPIOX_10 }, 1 },
+ { "spi_sclk", REG5, 0, { GPIOX_11 }, 1 },
+
+ /* GPIOZ */
+ { "eth_mdio", REG4, 23, { GPIOZ_0 }, 1 },
+ { "eth_mdc", REG4, 22, { GPIOZ_1 }, 1 },
+ { "eth_clk_rx_clk", REG4, 21, { GPIOZ_2 }, 1 },
+ { "eth_rx_dv", REG4, 20, { GPIOZ_3 }, 1 },
+ { "eth_rxd0", REG4, 19, { GPIOZ_4 }, 1 },
+ { "eth_rxd1", REG4, 18, { GPIOZ_5 }, 1 },
+ { "eth_rxd2", REG4, 17, { GPIOZ_6 }, 1 },
+ { "eth_rxd3", REG4, 16, { GPIOZ_7 }, 1 },
+ { "eth_rgmii_tx_clk", REG4, 15, { GPIOZ_8 }, 1 },
+ { "eth_tx_en", REG4, 14, { GPIOZ_9 }, 1 },
+ { "eth_txd0", REG4, 13, { GPIOZ_10 }, 1 },
+ { "eth_txd1", REG4, 12, { GPIOZ_11 }, 1 },
+ { "eth_txd2", REG4, 11, { GPIOZ_12 }, 1 },
+ { "eth_txd3", REG4, 10, { GPIOZ_13 }, 1 },
+ { "pwm_c", REG3, 20, { GPIOZ_15 }, 1 },
+ { "i2s_out_ch23_z", REG3, 26, { GPIOZ_5 }, 1 },
+ { "i2s_out_ch45_z", REG3, 25, { GPIOZ_6 }, 1 },
+ { "i2s_out_ch67_z", REG3, 24, { GPIOZ_7 }, 1 },
+ { "eth_link_led", REG4, 25, { GPIOZ_14 }, 1 },
+ { "eth_act_led", REG4, 24, { GPIOZ_15 }, 1 },
+
+ /* GPIOH */
+ { "hdmi_hpd", REG6, 31, { GPIOH_0 }, 1 },
+ { "hdmi_sda", REG6, 30, { GPIOH_1 }, 1 },
+ { "hdmi_scl", REG6, 29, { GPIOH_2 }, 1 },
+ { "i2s_am_clk", REG6, 26, { GPIOH_6 }, 1 },
+ { "i2s_out_ao_clk", REG6, 25, { GPIOH_7 }, 1 },
+ { "i2s_out_lr_clk", REG6, 24, { GPIOH_8 }, 1 },
+ { "i2s_out_ch01", REG6, 23, { GPIOH_9 }, 1 },
+ { "spdif_out_h", REG6, 28, { GPIOH_4 }, 1 },
+
+ /* GPIODV */
+ { "uart_tx_b", REG2, 16, { GPIODV_24 }, 1 },
+ { "uart_rx_b", REG2, 15, { GPIODV_25 }, 1 },
+ { "uart_cts_b", REG2, 14, { GPIODV_26 }, 1 },
+ { "uart_rts_b", REG2, 13, { GPIODV_27 }, 1 },
+ { "i2c_sda_c_dv18", REG1, 17, { GPIODV_18 }, 1 },
+ { "i2c_sck_c_dv19", REG1, 16, { GPIODV_19 }, 1 },
+ { "i2c_sda_a", REG1, 15, { GPIODV_24 }, 1 },
+ { "i2c_sck_a", REG1, 14, { GPIODV_25 }, 1 },
+ { "i2c_sda_b", REG1, 13, { GPIODV_26 }, 1 },
+ { "i2c_sck_b", REG1, 12, { GPIODV_27 }, 1 },
+ { "i2c_sda_c", REG1, 11, { GPIODV_28 }, 1 },
+ { "i2c_sck_c", REG1, 10, { GPIODV_29 }, 1 },
+ { "pwm_b", REG2, 11, { GPIODV_29 }, 1 },
+ { "pwm_d", REG2, 12, { GPIODV_28 }, 1 },
+ { "tsin_a_d0", REG2, 4, { GPIODV_0 }, 1 },
+ { "tsin_a_dp", REG2, 3, { GPIODV_1, GPIODV_2, GPIODV_3, GPIODV_4, GPIODV_5, GPIODV_6, GPIODV_7 }, 7 },
+ { "tsin_a_clk", REG2, 2, { GPIODV_8 }, 1 },
+ { "tsin_a_sop", REG2, 1, { GPIODV_9 }, 1 },
+ { "tsin_a_d_valid", REG2, 0, { GPIODV_10 }, 1 },
+ { "tsin_a_fail", REG1, 31, { GPIODV_11 }, 1 },
+
+ /* BOOT */
+ { "emmc_nand_d07", REG7, 31, { BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7 }, 8 },
+ { "emmc_clk", REG7, 30, { BOOT_8 }, 1 },
+ { "emmc_cmd", REG7, 29, { BOOT_10 }, 1 },
+ { "emmc_ds", REG7, 28, { BOOT_15 }, 1 },
+ { "nor_d", REG7, 13, { BOOT_11 }, 1 },
+ { "nor_q", REG7, 12, { BOOT_12 }, 1 },
+ { "nor_c", REG7, 11, { BOOT_13 }, 1 },
+ { "nor_cs", REG7, 10, { BOOT_15 }, 1 },
+ { "nand_ce0", REG7, 7, { BOOT_8 }, 1 },
+ { "nand_ce1", REG7, 6, { BOOT_9 }, 1 },
+ { "nand_rb0", REG7, 5, { BOOT_10 }, 1 },
+ { "nand_ale", REG7, 4, { BOOT_11 }, 1 },
+ { "nand_cle", REG7, 3, { BOOT_12 }, 1 },
+ { "nand_wen_clk", REG7, 2, { BOOT_13 }, 1 },
+ { "nand_ren_wr", REG7, 1, { BOOT_14 }, 1 },
+ { "nand_dqs", REG7, 0, { BOOT_15 }, 1 },
+
+ /* CARD */
+ { "sdcard_d1", REG6, 5, { CARD_0 }, 1 },
+ { "sdcard_d0", REG6, 4, { CARD_1 }, 1 },
+ { "sdcard_d3", REG6, 1, { CARD_4 }, 1 },
+ { "sdcard_d2", REG6, 0, { CARD_5 }, 1 },
+ { "sdcard_cmd", REG6, 2, { CARD_3 }, 1 },
+ { "sdcard_clk", REG6, 3, { CARD_2 }, 1 },
+
+ /* GPIOCLK */
+ { "pwm_f_clk", REG8, 30, { GPIOCLK_1 }, 1 },
+};
+
+static const struct meson_pinctrl_group mesongxl_aobus_groups[] = {
+ /* GPIOAO */
+ { "uart_tx_ao_b_0", AOREG0, 26, { GPIOAO_0 }, 1 },
+ { "uart_rx_ao_b_1", AOREG0, 25, { GPIOAO_1 }, 1 },
+ { "uart_tx_ao_b", AOREG0, 24, { GPIOAO_4 }, 1 },
+ { "uart_rx_ao_b", AOREG0, 23, { GPIOAO_5 }, 1 },
+ { "uart_tx_ao_a", AOREG0, 12, { GPIOAO_0 }, 1 },
+ { "uart_rx_ao_a", AOREG0, 11, { GPIOAO_1 }, 1 },
+ { "uart_cts_ao_a", AOREG0, 10, { GPIOAO_2 }, 1 },
+ { "uart_rts_ao_a", AOREG0, 9, { GPIOAO_3 }, 1 },
+ { "uart_cts_ao_b", AOREG0, 8, { GPIOAO_2 }, 1 },
+ { "uart_rts_ao_b", AOREG0, 7, { GPIOAO_3 }, 1 },
+ { "i2c_sck_ao", AOREG0, 6, { GPIOAO_4 }, 1 },
+ { "i2c_sda_ao", AOREG0, 5, { GPIOAO_5 }, 1 },
+ { "i2c_slave_sck_ao", AOREG0, 2, { GPIOAO_4 }, 1 },
+ { "i2c_slave_sda_ao", AOREG0, 1, { GPIOAO_5 }, 1 },
+ { "remote_input_ao", AOREG0, 0, { GPIOAO_7 }, 1 },
+ { "pwm_ao_a_3", AOREG0, 22, { GPIOAO_3 }, 1 },
+ { "pwm_ao_b_6", AOREG0, 18, { GPIOAO_6 }, 1 },
+ { "pwm_ao_a_8", AOREG0, 17, { GPIOAO_8 }, 1 },
+ { "pwm_ao_b", AOREG0, 3, { GPIOAO_9 }, 1 },
+ { "i2s_out_ch23_ao", AOREG1, 0, { GPIOAO_8 }, 1 },
+ { "i2s_out_ch45_ao", AOREG1, 1, { GPIOAO_9 }, 1 },
+ { "spdif_out_ao_6", AOREG0, 16, { GPIOAO_6 }, 1 },
+ { "spdif_out_ao_9", AOREG0, 4, { GPIOAO_9 }, 1 },
+ { "ao_cec", AOREG0, 15, { GPIOAO_8 }, 1 },
+ { "ee_cec", AOREG0, 14, { GPIOAO_8 }, 1 },
+
+ /* TEST_N */
+ { "i2s_out_ch67_ao", AOREG1, 2, { GPIO_TEST_N }, 1 },
+
+};
+
+const struct meson_pinctrl_config mesongxl_periphs_pinctrl_config = {
+ .name = "Meson GXL periphs GPIO",
+ .groups = mesongxl_periphs_groups,
+ .ngroups = __arraycount(mesongxl_periphs_groups),
+ .gpios = mesongxl_periphs_gpios,
+ .ngpios = __arraycount(mesongxl_periphs_gpios),
+};
+
+const struct meson_pinctrl_config mesongxl_aobus_pinctrl_config = {
+ .name = "Meson GXL AO GPIO",
+ .groups = mesongxl_aobus_groups,
+ .ngroups = __arraycount(mesongxl_aobus_groups),
+ .gpios = mesongxl_aobus_gpios,
+ .ngpios = __arraycount(mesongxl_aobus_gpios),
+};
Index: src/sys/arch/arm/amlogic/mesongxl_usb2phy.c
diff -u /dev/null src/sys/arch/arm/amlogic/mesongxl_usb2phy.c:1.1
--- /dev/null Fri Apr 19 19:07:56 2019
+++ src/sys/arch/arm/amlogic/mesongxl_usb2phy.c Fri Apr 19 19:07:56 2019
@@ -0,0 +1,191 @@
+/* $NetBSD: mesongxl_usb2phy.c,v 1.1 2019/04/19 19:07:56 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2019 Jared McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(0, "$NetBSD: mesongxl_usb2phy.c,v 1.1 2019/04/19 19:07:56 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/time.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#define USB2PHY_REG0 0x00
+#define REG0_POWER_ON_RESET __BIT(22)
+#define REG0_ID_PULLUP __BIT(13)
+#define REG0_DP_PULLDOWN __BIT(6)
+#define REG0_DM_PULLDOWN __BIT(5)
+
+static int mesongxl_usb2phy_match(device_t, cfdata_t, void *);
+static void mesongxl_usb2phy_attach(device_t, device_t, void *);
+
+static const char *compatible[] = {
+ "amlogic,meson-gxl-usb2-phy",
+ NULL
+};
+
+struct mesongxl_usb2phy_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+ int sc_phandle;
+ struct clk *sc_clk;
+ struct fdtbus_reset *sc_rst;
+ struct fdtbus_regulator *sc_supply;
+};
+
+#define PHY_READ(sc, reg) \
+ bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
+#define PHY_WRITE(sc, reg, val) \
+ bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
+
+CFATTACH_DECL_NEW(mesongxl_usb2phy, sizeof(struct mesongxl_usb2phy_softc),
+ mesongxl_usb2phy_match, mesongxl_usb2phy_attach, NULL, NULL);
+
+static void *
+mesongxl_usb2phy_acquire(device_t dev, const void *data, size_t len)
+{
+ if (len != 0)
+ return NULL;
+
+ return (void *)(uintptr_t)1;
+}
+
+static void
+mesongxl_usb2phy_release(device_t dev, void *priv)
+{
+}
+
+static int
+mesongxl_usb2phy_enable(device_t dev, void *priv, bool enable)
+{
+ struct mesongxl_usb2phy_softc * const sc = device_private(dev);
+ uint32_t val;
+
+ if (enable) {
+ /* Power on PHY */
+ val = PHY_READ(sc, USB2PHY_REG0);
+ val &= ~REG0_POWER_ON_RESET;
+ PHY_WRITE(sc, USB2PHY_REG0, val);
+
+ /* Configure PHY for host mode */
+ val = PHY_READ(sc, USB2PHY_REG0);
+ val |= REG0_DM_PULLDOWN;
+ val |= REG0_DP_PULLDOWN;
+ val &= ~REG0_ID_PULLUP;
+ PHY_WRITE(sc, USB2PHY_REG0, val);
+
+ /* Reset the PHY */
+ val = PHY_READ(sc, USB2PHY_REG0);
+ val |= REG0_POWER_ON_RESET;
+ PHY_WRITE(sc, USB2PHY_REG0, val);
+ delay(500);
+ val = PHY_READ(sc, USB2PHY_REG0);
+ val &= ~REG0_POWER_ON_RESET;
+ PHY_WRITE(sc, USB2PHY_REG0, val);
+ delay(500);
+
+ if (sc->sc_supply != NULL) {
+ if (fdtbus_regulator_enable(sc->sc_supply) != 0)
+ aprint_error(": couldn't enable supply\n");
+ }
+ } else {
+ /* Power off PHY */
+ val = PHY_READ(sc, USB2PHY_REG0);
+ val |= REG0_POWER_ON_RESET;
+ PHY_WRITE(sc, USB2PHY_REG0, val);
+ }
+
+ return 0;
+}
+
+const struct fdtbus_phy_controller_func mesongxl_usb2phy_funcs = {
+ .acquire = mesongxl_usb2phy_acquire,
+ .release = mesongxl_usb2phy_release,
+ .enable = mesongxl_usb2phy_enable,
+};
+
+static int
+mesongxl_usb2phy_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct fdt_attach_args * const faa = aux;
+
+ return of_match_compatible(faa->faa_phandle, compatible);
+}
+
+static void
+mesongxl_usb2phy_attach(device_t parent, device_t self, void *aux)
+{
+ struct mesongxl_usb2phy_softc * const sc = device_private(self);
+ struct fdt_attach_args * const faa = aux;
+ const int phandle = faa->faa_phandle;
+ bus_addr_t addr;
+ bus_size_t size;
+
+ sc->sc_dev = self;
+ sc->sc_bst = faa->faa_bst;
+ sc->sc_phandle = phandle;
+
+ if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
+ aprint_error(": couldn't get registers\n");
+ return;
+ }
+ if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
+ aprint_error(": couldn't map registers\n");
+ return;
+ }
+
+ sc->sc_clk = fdtbus_clock_get_index(phandle, 0);
+ if (sc->sc_clk == NULL) {
+ aprint_error(": couldn't get clock\n");
+ return;
+ }
+ sc->sc_rst = fdtbus_reset_get_index(phandle, 0);
+
+ if (sc->sc_rst != NULL) {
+ if (fdtbus_reset_deassert(sc->sc_rst) != 0) {
+ aprint_error(": couldn't de-assert reset\n");
+ return;
+ }
+ }
+ if (clk_enable(sc->sc_clk) != 0) {
+ aprint_error(": couldn't enable clock\n");
+ return;
+ }
+
+ sc->sc_supply = fdtbus_regulator_acquire(phandle, "phy-supply");
+
+ aprint_naive("\n");
+ aprint_normal(": USB2 PHY\n");
+
+ fdtbus_register_phy_controller(self, phandle, &mesongxl_usb2phy_funcs);
+}
Index: src/sys/arch/arm/amlogic/mesongxl_usb3phy.c
diff -u /dev/null src/sys/arch/arm/amlogic/mesongxl_usb3phy.c:1.1
--- /dev/null Fri Apr 19 19:07:56 2019
+++ src/sys/arch/arm/amlogic/mesongxl_usb3phy.c Fri Apr 19 19:07:56 2019
@@ -0,0 +1,223 @@
+/* $NetBSD: mesongxl_usb3phy.c,v 1.1 2019/04/19 19:07:56 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2019 Jared McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(0, "$NetBSD: mesongxl_usb3phy.c,v 1.1 2019/04/19 19:07:56 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/time.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#define USB3PHY_REG0 0x00
+#define REG0_U2D_ACT __BIT(31)
+
+#define USB3PHY_REG1 0x04
+#define REG1_U3H_FLADJ_30MHZ_REG __BITS(24,19)
+
+#define USB3PHY_REG4 0x10
+#define REG4_P21_SLEEP_M0 __BIT(1)
+
+#define USB3PHY_REG5 0x14
+#define REG5_ID_DIG_TH __BITS(15,8)
+#define REG5_ID_DIG_EN_1 __BIT(5)
+#define REG5_ID_DIG_EN_0 __BIT(4)
+
+static int mesongxl_usb3phy_match(device_t, cfdata_t, void *);
+static void mesongxl_usb3phy_attach(device_t, device_t, void *);
+
+static const char *compatible[] = {
+ "amlogic,meson-gxl-usb3-phy",
+ NULL
+};
+
+struct mesongxl_usb3phy_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+ int sc_phandle;
+ struct clk *sc_clk_phy;
+ struct clk *sc_clk_peripheral;
+};
+
+#define PHY_READ(sc, reg) \
+ bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
+#define PHY_WRITE(sc, reg, val) \
+ bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
+
+CFATTACH_DECL_NEW(mesongxl_usb3phy, sizeof(struct mesongxl_usb3phy_softc),
+ mesongxl_usb3phy_match, mesongxl_usb3phy_attach, NULL, NULL);
+
+static void *
+mesongxl_usb3phy_acquire(device_t dev, const void *data, size_t len)
+{
+ if (len != 0)
+ return NULL;
+
+ return (void *)(uintptr_t)1;
+}
+
+static void
+mesongxl_usb3phy_release(device_t dev, void *priv)
+{
+}
+
+static int
+mesongxl_usb3phy_enable(device_t dev, void *priv, bool enable)
+{
+ struct mesongxl_usb3phy_softc * const sc = device_private(dev);
+ uint32_t val;
+
+ if (enable) {
+ /* Power on PHY */
+ val = PHY_READ(sc, USB3PHY_REG5);
+ val |= REG5_ID_DIG_EN_0;
+ val |= REG5_ID_DIG_EN_1;
+ val &= ~REG5_ID_DIG_TH;
+ val |= __SHIFTIN(0xff, REG5_ID_DIG_TH);
+ PHY_WRITE(sc, USB3PHY_REG5, val);
+
+ /* Set host mode */
+ val = PHY_READ(sc, USB3PHY_REG0);
+ val &= ~REG0_U2D_ACT;
+ PHY_WRITE(sc, USB3PHY_REG0, val);
+
+ val = PHY_READ(sc, USB3PHY_REG4);
+ val &= ~REG4_P21_SLEEP_M0;
+ PHY_WRITE(sc, USB3PHY_REG4, val);
+ } else {
+ /* Power off PHY */
+ val = PHY_READ(sc, USB3PHY_REG5);
+ val &= ~REG5_ID_DIG_EN_0;
+ val &= ~REG5_ID_DIG_EN_1;
+ PHY_WRITE(sc, USB3PHY_REG5, val);
+ }
+
+ return 0;
+}
+
+const struct fdtbus_phy_controller_func mesongxl_usb3phy_funcs = {
+ .acquire = mesongxl_usb3phy_acquire,
+ .release = mesongxl_usb3phy_release,
+ .enable = mesongxl_usb3phy_enable,
+};
+
+static void
+mesongxl_usb3phy_init(struct mesongxl_usb3phy_softc *sc)
+{
+ uint32_t val;
+
+ val = PHY_READ(sc, USB3PHY_REG1);
+ val &= ~REG1_U3H_FLADJ_30MHZ_REG;
+ val |= __SHIFTIN(0x20, REG1_U3H_FLADJ_30MHZ_REG);
+ PHY_WRITE(sc, USB3PHY_REG1, val);
+}
+
+static int
+mesongxl_usb3phy_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct fdt_attach_args * const faa = aux;
+
+ return of_match_compatible(faa->faa_phandle, compatible);
+}
+
+static void
+mesongxl_usb3phy_attach(device_t parent, device_t self, void *aux)
+{
+ struct mesongxl_usb3phy_softc * const sc = device_private(self);
+ struct fdt_attach_args * const faa = aux;
+ const int phandle = faa->faa_phandle;
+ struct fdtbus_regulator *supply;
+ struct fdtbus_reset *rst;
+ bus_addr_t addr;
+ bus_size_t size;
+ u_int n;
+
+ sc->sc_dev = self;
+ sc->sc_bst = faa->faa_bst;
+ sc->sc_phandle = phandle;
+
+ if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
+ aprint_error(": couldn't get registers\n");
+ return;
+ }
+ if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
+ aprint_error(": couldn't map registers\n");
+ return;
+ }
+
+ sc->sc_clk_phy = fdtbus_clock_get(phandle, "phy");
+ if (sc->sc_clk_phy == NULL) {
+ aprint_error(": couldn't get phy clock\n");
+ return;
+ }
+#if notyet
+ sc->sc_clk_peripheral = fdtbus_clock_get(phandle, "peripheral");
+ if (sc->sc_clk_peripheral == NULL) {
+ aprint_error(": couldn't get peripheral clock\n");
+ return;
+ }
+#endif
+
+ for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++) {
+ if (fdtbus_reset_deassert(rst) != 0) {
+ aprint_error(": couldn't de-assert reset #%d\n", n);
+ return;
+ }
+ }
+ if (clk_enable(sc->sc_clk_phy) != 0) {
+ aprint_error(": couldn't enable phy clock\n");
+ return;
+ }
+#if notyet
+ if (clk_enable(sc->sc_clk_peripheral) != 0) {
+ aprint_error(": couldn't enable peripheral clock\n");
+ return;
+ }
+#endif
+
+ supply = fdtbus_regulator_acquire(phandle, "phy-supply");
+ if (supply != NULL) {
+ if (fdtbus_regulator_enable(supply) != 0) {
+ aprint_error(": couldn't enable supply\n");
+ return;
+ }
+ }
+
+ aprint_naive("\n");
+ aprint_normal(": USB3 PHY\n");
+
+ mesongxl_usb3phy_init(sc);
+
+ fdtbus_register_phy_controller(self, phandle, &mesongxl_usb3phy_funcs);
+}
