Module Name: src
Committed By: maxv
Date: Sat May 4 07:20:22 UTC 2019
Modified Files:
src/sys/arch/amd64/amd64: cpufunc.S
src/sys/arch/i386/i386: cpufunc.S i386func.S
src/sys/arch/x86/include: cpufunc.h
src/sys/arch/xen/x86: xenfunc.c
Log Message:
More inlined ASM. While here switch to proper types.
To generate a diff of this commit:
cvs rdiff -u -r1.38 -r1.39 src/sys/arch/amd64/amd64/cpufunc.S
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/i386/i386/cpufunc.S
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/i386/i386/i386func.S
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/x86/include/cpufunc.h
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/xen/x86/xenfunc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/amd64/amd64/cpufunc.S
diff -u src/sys/arch/amd64/amd64/cpufunc.S:1.38 src/sys/arch/amd64/amd64/cpufunc.S:1.39
--- src/sys/arch/amd64/amd64/cpufunc.S:1.38 Wed May 1 15:17:49 2019
+++ src/sys/arch/amd64/amd64/cpufunc.S Sat May 4 07:20:22 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.S,v 1.38 2019/05/01 15:17:49 maxv Exp $ */
+/* $NetBSD: cpufunc.S,v 1.39 2019/05/04 07:20:22 maxv Exp $ */
/*
* Copyright (c) 1998, 2007, 2008 The NetBSD Foundation, Inc.
@@ -88,58 +88,8 @@ ENTRY(ltr)
ltr %di
ret
END(ltr)
-
-ENTRY(lcr0)
- movq %rdi, %cr0
- ret
-END(lcr0)
-
-ENTRY(rcr0)
- movq %cr0, %rax
- ret
-END(rcr0)
-
-ENTRY(lcr2)
- movq %rdi, %cr2
- ret
-END(lcr2)
-
-ENTRY(rcr2)
- movq %cr2, %rax
- ret
-END(rcr2)
-
-ENTRY(lcr3)
- movq %rdi, %cr3
- ret
-END(lcr3)
-
-ENTRY(rcr3)
- movq %cr3, %rax
- ret
-END(rcr3)
#endif
-ENTRY(lcr4)
- movq %rdi, %cr4
- ret
-END(lcr4)
-
-ENTRY(rcr4)
- movq %cr4, %rax
- ret
-END(rcr4)
-
-ENTRY(lcr8)
- movq %rdi, %cr8
- ret
-END(lcr8)
-
-ENTRY(rcr8)
- movq %cr8, %rax
- ret
-END(rcr8)
-
/*
* Big hammer: flush all TLB entries, including ones from PTE's
* with the G bit set. This should only be necessary if TLB
@@ -177,76 +127,6 @@ ENTRY(tlbflush)
ret
END(tlbflush)
-ENTRY(ldr0)
- movq %rdi, %dr0
- ret
-END(ldr0)
-
-ENTRY(rdr0)
- movq %dr0, %rax
- ret
-END(rdr0)
-
-ENTRY(ldr1)
- movq %rdi, %dr1
- ret
-END(ldr1)
-
-ENTRY(rdr1)
- movq %dr1, %rax
- ret
-END(rdr1)
-
-ENTRY(ldr2)
- movq %rdi, %dr2
- ret
-END(ldr2)
-
-ENTRY(rdr2)
- movq %dr2, %rax
- ret
-END(rdr2)
-
-ENTRY(ldr3)
- movq %rdi, %dr3
- ret
-END(ldr3)
-
-ENTRY(rdr3)
- movq %dr3, %rax
- ret
-END(rdr3)
-
-ENTRY(ldr6)
- movq %rdi, %dr6
- ret
-END(ldr6)
-
-ENTRY(rdr6)
- movq %dr6, %rax
- ret
-END(rdr6)
-
-ENTRY(ldr7)
- movq %rdi, %dr7
- ret
-END(ldr7)
-
-ENTRY(rdr7)
- movq %dr7, %rax
- ret
-END(rdr7)
-
-ENTRY(x86_disable_intr)
- cli
- ret
-END(x86_disable_intr)
-
-ENTRY(x86_enable_intr)
- sti
- ret
-END(x86_enable_intr)
-
ENTRY(x86_read_flags)
pushfq
popq %rax
@@ -469,21 +349,6 @@ ENTRY(x86_cpuid2)
ret
END(x86_cpuid2)
-ENTRY(x86_getss)
- movl %ss, %eax
- ret
-END(x86_getss)
-
-ENTRY(fnclex)
- fnclex
- ret
-END(fnclex)
-
-ENTRY(fninit)
- fninit
- ret
-END(fninit)
-
ENTRY(fnsave)
fnsave (%rdi)
ret
@@ -664,21 +529,6 @@ ENTRY(outsl)
ret
END(outsl)
-ENTRY(setds)
- movw %di, %ds
- ret
-END(setds)
-
-ENTRY(setes)
- movw %di, %es
- ret
-END(setes)
-
-ENTRY(setfs)
- movw %di, %fs
- ret
-END(setfs)
-
#ifndef XENPV
ENTRY(setusergs)
CLI(ax)
Index: src/sys/arch/i386/i386/cpufunc.S
diff -u src/sys/arch/i386/i386/cpufunc.S:1.30 src/sys/arch/i386/i386/cpufunc.S:1.31
--- src/sys/arch/i386/i386/cpufunc.S:1.30 Wed May 1 15:17:49 2019
+++ src/sys/arch/i386/i386/cpufunc.S Sat May 4 07:20:22 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.S,v 1.30 2019/05/01 15:17:49 maxv Exp $ */
+/* $NetBSD: cpufunc.S,v 1.31 2019/05/04 07:20:22 maxv Exp $ */
/*-
* Copyright (c) 1998, 2007 The NetBSD Foundation, Inc.
@@ -38,7 +38,7 @@
#include <sys/errno.h>
#include <machine/asm.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.S,v 1.30 2019/05/01 15:17:49 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.S,v 1.31 2019/05/04 07:20:22 maxv Exp $");
#include "opt_xen.h"
@@ -73,22 +73,6 @@ ENTRY(lidt)
END(lidt)
#endif /* XENPV */
-ENTRY(rcr3)
- movl %cr3, %eax
- ret
-END(rcr3)
-
-ENTRY(lcr4)
- movl 4(%esp), %eax
- movl %eax, %cr4
- ret
-END(lcr4)
-
-ENTRY(rcr4)
- movl %cr4, %eax
- ret
-END(rcr4)
-
ENTRY(x86_read_flags)
pushfl
popl %eax
@@ -276,21 +260,6 @@ ENTRY(x86_cpuid2)
ret
END(x86_cpuid2)
-ENTRY(x86_getss)
- movl %ss, %eax
- ret
-END(x86_getss)
-
-ENTRY(fnclex)
- fnclex
- ret
-END(fnclex)
-
-ENTRY(fninit)
- fninit
- ret
-END(fninit)
-
ENTRY(fnsave)
movl 4(%esp), %eax
fnsave (%eax)
Index: src/sys/arch/i386/i386/i386func.S
diff -u src/sys/arch/i386/i386/i386func.S:1.20 src/sys/arch/i386/i386/i386func.S:1.21
--- src/sys/arch/i386/i386/i386func.S:1.20 Sun Jan 6 14:35:31 2019
+++ src/sys/arch/i386/i386/i386func.S Sat May 4 07:20:22 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: i386func.S,v 1.20 2019/01/06 14:35:31 cherry Exp $ */
+/* $NetBSD: i386func.S,v 1.21 2019/05/04 07:20:22 maxv Exp $ */
/*-
* Copyright (c) 1998, 2007, 2008 The NetBSD Foundation, Inc.
@@ -36,7 +36,7 @@
*/
#include <machine/asm.h>
-__KERNEL_RCSID(0, "$NetBSD: i386func.S,v 1.20 2019/01/06 14:35:31 cherry Exp $");
+__KERNEL_RCSID(0, "$NetBSD: i386func.S,v 1.21 2019/05/04 07:20:22 maxv Exp $");
#include <machine/specialreg.h>
#include <machine/segments.h>
@@ -66,23 +66,6 @@ ENTRY(ltr)
ret
END(ltr)
-ENTRY(lcr0)
- movl 4(%esp), %eax
- movl %eax, %cr0
- ret
-END(lcr0)
-
-ENTRY(rcr0)
- movl %cr0, %eax
- ret
-END(rcr0)
-
-ENTRY(lcr3)
- movl 4(%esp), %eax
- movl %eax, %cr3
- ret
-END(lcr3)
-
/*
* Big hammer: flush all TLB entries, including ones from PTE's
* with the G bit set. This should only be necessary if TLB
@@ -123,98 +106,11 @@ ENTRY(tlbflush)
ret
END(tlbflush)
-ENTRY(ldr0)
- movl 4(%esp), %eax
- movl %eax, %dr0
- ret
-END(ldr0)
-
-ENTRY(rdr0)
- movl %dr0, %eax
- ret
-END(rdr0)
-
-ENTRY(ldr1)
- movl 4(%esp), %eax
- movl %eax, %dr1
- ret
-END(ldr1)
-
-ENTRY(rdr1)
- movl %dr1, %eax
- ret
-END(rdr1)
-
-ENTRY(ldr2)
- movl 4(%esp), %eax
- movl %eax, %dr2
- ret
-END(ldr2)
-
-ENTRY(rdr2)
- movl %dr2, %eax
- ret
-END(rdr2)
-
-ENTRY(ldr3)
- movl 4(%esp), %eax
- movl %eax, %dr3
- ret
-END(ldr3)
-
-ENTRY(rdr3)
- movl %dr3, %eax
- ret
-END(rdr3)
-
-ENTRY(ldr6)
- movl 4(%esp), %eax
- movl %eax, %dr6
- ret
-END(ldr6)
-
-ENTRY(rdr6)
- movl %dr6, %eax
- ret
-END(rdr6)
-
-ENTRY(ldr7)
- movl 4(%esp), %eax
- movl %eax, %dr7
- ret
-END(ldr7)
-
-ENTRY(rdr7)
- movl %dr7, %eax
- ret
-END(rdr7)
-
-ENTRY(rcr2)
- movl %cr2, %eax
- ret
-END(rcr2)
-
-ENTRY(lcr2)
- movl 4(%esp), %eax
- movl %eax, %cr2
- ret
-END(lcr2)
-
ENTRY(wbinvd)
wbinvd
ret
END(wbinvd)
-ENTRY(x86_disable_intr)
- cli
- ret
-END(x86_disable_intr)
-
-ENTRY(x86_enable_intr)
- sti
- ret
-END(x86_enable_intr)
-
/*
* void lgdt(struct region_descriptor *rdp);
*
Index: src/sys/arch/x86/include/cpufunc.h
diff -u src/sys/arch/x86/include/cpufunc.h:1.26 src/sys/arch/x86/include/cpufunc.h:1.27
--- src/sys/arch/x86/include/cpufunc.h:1.26 Wed May 1 15:17:49 2019
+++ src/sys/arch/x86/include/cpufunc.h Sat May 4 07:20:22 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.h,v 1.26 2019/05/01 15:17:49 maxv Exp $ */
+/* $NetBSD: cpufunc.h,v 1.27 2019/05/04 07:20:22 maxv Exp $ */
/*
* Copyright (c) 1998, 2007, 2019 The NetBSD Foundation, Inc.
@@ -95,47 +95,160 @@ void lidt(struct region_descriptor *);
void lldt(u_short);
void ltr(u_short);
-void lcr0(u_long);
-u_long rcr0(void);
-void lcr2(vaddr_t);
-vaddr_t rcr2(void);
-void lcr3(vaddr_t);
-vaddr_t rcr3(void);
-void lcr4(vaddr_t);
-vaddr_t rcr4(void);
-void lcr8(vaddr_t);
-vaddr_t rcr8(void);
-
-register_t rdr0(void);
-void ldr0(register_t);
-register_t rdr1(void);
-void ldr1(register_t);
-register_t rdr2(void);
-void ldr2(register_t);
-register_t rdr3(void);
-void ldr3(register_t);
-register_t rdr6(void);
-void ldr6(register_t);
-register_t rdr7(void);
-void ldr7(register_t);
-
-u_int x86_getss(void);
-void setds(int);
-void setes(int);
-void setfs(int);
+static inline uint16_t
+x86_getss(void)
+{
+ uint16_t val;
+
+ asm volatile (
+ "mov %%ss,%[val]"
+ : [val] "=r" (val)
+ :
+ );
+ return val;
+}
+
+static inline void
+setds(uint16_t val)
+{
+ asm volatile (
+ "mov %[val],%%ds"
+ :
+ : [val] "r" (val)
+ );
+}
+
+static inline void
+setes(uint16_t val)
+{
+ asm volatile (
+ "mov %[val],%%es"
+ :
+ : [val] "r" (val)
+ );
+}
+
+static inline void
+setfs(uint16_t val)
+{
+ asm volatile (
+ "mov %[val],%%fs"
+ :
+ : [val] "r" (val)
+ );
+}
+
void setusergs(int);
/* -------------------------------------------------------------------------- */
+#define FUNC_CR(crnum) \
+ static inline void lcr##crnum(register_t val) \
+ { \
+ asm volatile ( \
+ "mov %[val],%%cr" #crnum \
+ : \
+ : [val] "r" (val) \
+ ); \
+ } \
+ static inline register_t rcr##crnum(void) \
+ { \
+ register_t val; \
+ asm volatile ( \
+ "mov %%cr" #crnum ",%[val]" \
+ : [val] "=r" (val) \
+ : \
+ ); \
+ return val; \
+ }
+
+#define PROTO_CR(crnum) \
+ void lcr##crnum(register_t); \
+ register_t rcr##crnum(void);
+
+#ifndef XENPV
+FUNC_CR(0)
+FUNC_CR(2)
+FUNC_CR(3)
+#else
+PROTO_CR(0)
+PROTO_CR(2)
+PROTO_CR(3)
+#endif
+
+FUNC_CR(4)
+FUNC_CR(8)
+
+/* -------------------------------------------------------------------------- */
+
+#define FUNC_DR(drnum) \
+ static inline void ldr##drnum(register_t val) \
+ { \
+ asm volatile ( \
+ "mov %[val],%%dr" #drnum \
+ : \
+ : [val] "r" (val) \
+ ); \
+ } \
+ static inline register_t rdr##drnum(void) \
+ { \
+ register_t val; \
+ asm volatile ( \
+ "mov %%dr" #drnum ",%[val]" \
+ : [val] "=r" (val) \
+ : \
+ ); \
+ return val; \
+ }
+
+#define PROTO_DR(drnum) \
+ register_t rdr##drnum(void); \
+ void ldr##drnum(register_t);
+
+#ifndef XENPV
+FUNC_DR(0)
+FUNC_DR(1)
+FUNC_DR(2)
+FUNC_DR(3)
+FUNC_DR(6)
+FUNC_DR(7)
+#else
+PROTO_DR(0)
+PROTO_DR(1)
+PROTO_DR(2)
+PROTO_DR(3)
+PROTO_DR(6)
+PROTO_DR(7)
+#endif
+
+/* -------------------------------------------------------------------------- */
+
union savefpu;
-void fnclex(void);
-void fninit(void);
+
+static inline void
+fninit(void)
+{
+ asm volatile ("fninit");
+}
+
+static inline void
+fnclex(void)
+{
+ asm volatile ("fnclex");
+}
+
void fnsave(union savefpu *);
void fnstcw(uint16_t *);
uint16_t fngetsw(void);
void fnstsw(uint16_t *);
void frstor(const union savefpu *);
-void clts(void);
+
+static inline void
+clts(void)
+{
+ asm volatile ("clts");
+}
+
void stts(void);
void fxsave(union savefpu *);
void fxrstor(const union savefpu *);
@@ -178,9 +291,19 @@ void xsaveopt(union savefpu *, uint64_t)
/* -------------------------------------------------------------------------- */
+static inline void
+x86_disable_intr(void)
+{
+ asm volatile ("cli");
+}
+
+static inline void
+x86_enable_intr(void)
+{
+ asm volatile ("sti");
+}
+
/* Use read_psl, write_psl when saving and restoring interrupt state. */
-void x86_disable_intr(void);
-void x86_enable_intr(void);
u_long x86_read_psl(void);
void x86_write_psl(u_long);
@@ -194,10 +317,8 @@ void x86_reset(void);
/*
* Some of the undocumented AMD64 MSRs need a 'passcode' to access.
- *
* See LinuxBIOSv2: src/cpu/amd/model_fxx/model_fxx_init.c
*/
-
#define OPTERON_MSR_PASSCODE 0x9c5a203aU
static inline uint64_t
Index: src/sys/arch/xen/x86/xenfunc.c
diff -u src/sys/arch/xen/x86/xenfunc.c:1.24 src/sys/arch/xen/x86/xenfunc.c:1.25
--- src/sys/arch/xen/x86/xenfunc.c:1.24 Sun Jan 6 14:35:31 2019
+++ src/sys/arch/xen/x86/xenfunc.c Sat May 4 07:20:22 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: xenfunc.c,v 1.24 2019/01/06 14:35:31 cherry Exp $ */
+/* $NetBSD: xenfunc.c,v 1.25 2019/05/04 07:20:22 maxv Exp $ */
/*
* Copyright (c) 2004 Christian Limpach.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: xenfunc.c,v 1.24 2019/01/06 14:35:31 cherry Exp $");
+__KERNEL_RCSID(0, "$NetBSD: xenfunc.c,v 1.25 2019/05/04 07:20:22 maxv Exp $");
#include <sys/param.h>
@@ -124,12 +124,12 @@ ltr(u_short sel)
}
void
-lcr0(u_long val)
+lcr0(register_t val)
{
panic("XXX lcr0 not supported\n");
}
-u_long
+register_t
rcr0(void)
{
/* XXX: handle X86_CR0_TS ? */
@@ -250,7 +250,7 @@ wbinvd(void)
xpq_flush_cache();
}
-vaddr_t
+register_t
rcr2(void)
{
return curcpu()->ci_vcpu->arch.cr2;
